Verilog 无法弄清楚为什么 reg 总是 X

Question

我正在尝试使用 verilog 进行 VGA 输出，但我似乎无法弄清楚为什么 r_hcount 保持 X。模拟波形显示 r_vcount 正在正确重置为 0 但是由于某种原因 r_hcount 永远不会重置为 0。我不明白为什么...

Verilog 代码：

module m_VGA640x480(
  input  wire        iw_clock,
  input  wire        iw_pix_stb,
  input  wire        iw_rst,
  output wire        ow_hs,
  output wire        ow_vs,
  output wire        ow_blanking,
  output wire        ow_active,
  output wire        ow_screenend,
  output wire        ow_animate,
  output wire  [9:0] ow_x,
  output wire  [9:0] ow_y
  );
  localparam HS_STA = 16;
  localparam HS_END = 16 + 96;
  localparam HA_STA = 16 + 96 + 48;
  localparam VS_STA = 480 + 11;
  localparam VS_END = 400 + 11 + 2;
  localparam VA_END = 480;
  localparam LINE   = 800;
  localparam SCREEN = 524;

  reg [9:0] r_hcount;
  reg [9:0] r_vcount;

  assign ow_hs = ~((r_hcount >= HS_STA) & (r_hcount < HS_END));
  assign ow_vs = ~((r_vcount >= VS_STA) & (r_vcount < VS_END));

  assign ow_x = (r_hcount <  HA_STA) ? 0 : (r_hcount - HA_STA);
  assign ow_y = (r_vcount >= VA_END) ? (VA_END - 1) : (r_vcount);

  assign ow_blanking = ((r_hcount < HA_STA) | (r_vcount > VA_END - 1));

  assign ow_active = ~((r_hcount < HA_STA) | (r_vcount > VA_END - 1));

  assign ow_screenend = ((r_vcount == SCREEN - 1) & (r_hcount == LINE));

  assign ow_animate = ((r_vcount ==VA_END - 1) & (r_hcount == LINE));

  always @(posedge iw_clock)
  begin
    if (iw_rst)
    begin
      r_hcount <= 0;
      r_vcount <= 0;
    end
    if (iw_pix_stb)
    begin
      if (r_hcount == LINE)
      begin
        r_hcount <= 0;
        r_vcount <= r_vcount + 1;
      end
      else
        r_hcount <= r_hcount + 1;

      if (r_vcount == SCREEN)
        r_vcount <= 0;
    end
  end
endmodule

这是模拟的结果。 r_hcount 有问题...当重置为 1 时，代码应该将两个计数器都设置为 0，但由于某种原因它没有重置为 0。请帮助。

Wavefrorm

Answer 1

从您的工作中，我注意到有一点可能会导致该问题

always @(posedge iw_clock)
begin
    if (iw_rst)
    //you define r_hcount <= 0 here
    .....
    if (iw_pix_stb) //<== another condition
    // r_hcount <= 0 is also defined here

所以如果 posedge clock 发生了，r_hcount 可能会在这里被窃听。我建议应该这样做

 else if (iw_pix_stb) <=== else if here

祝你好运。

Answer 2

在对代码进行了更多修改之后，我发现这是因为 r_hcount <= 0 被 r_hcount <= r_hcount + 1 覆盖，这将设置r_hcount 到 X。这是因为两个时钟输入的频率相同。

以后要注意点...

Verilog 无法弄清楚为什么 reg 总是 X

Verilog can't figure out why a reg is always X

verilog

waveform

fpga