在结构和行为架构中访问信号
Accessing a signal in both structural and behavioural architecture
我已经定义了一个模块的结构体系结构例如
architecture structural of my_entity is
signal counter : integer := 0;
begin
MODULE port map(......count => counter.....); --this is an inout port
end structural;
我想实现一个计数器,它根据输入信号 signalIn
到 my_entity
的变化而递增,并将此计数器值传输到 MODULE
。
有没有办法在 my_entity
的行为架构中增加此 counter
信号?例如
architecture Behavioural of my_entity is
begin
process(signalIn)
begin
counter <= counter + 1;
end process;
end Behavioural;
当然,在此行为架构中,据报告 counter
未声明。我该如何解决这个问题?
您的问题在 counter
的一个体系结构中显示声明时没有显示信号 inSignal
的声明(这是一个信号,因为它显示在进程的敏感列表中)。您也不显示 MODULE
.
的组件声明
my_enity is
end entity;
architecture structural of my_entity is
signal counter: integer := 0;
begin
UNLABELLED_COMPONENT_INSTANTIATION: -- presuming count is declared mode in
MODULE port map(......count => counter.....); --this is an inout port
UNLABELLED_PROCESS:
process (inSignal)
begin
counter <= counter + 1;
end architecture structural;
您可以使用进程来操作计数器(请注意,它没有以易于合成的形式显示)或 不同[=21= 的单独组件实例] 实现计数器的实体架构对。
architecture pure_structural of my_entity is
signal counter: integer := 0;
begin
UNLABELLED_COMPONENT_INSTANTIATION: -- presuming count is declared mode in
MODULE port map(......count => counter.....); --this is an inout port
COUNTER_COMPONENT:
SOME_COUNTER port map (trigger => signalIn, count => counter);
-- where in this case count is mode out
end architecture pure_structural;
我已经定义了一个模块的结构体系结构例如
architecture structural of my_entity is
signal counter : integer := 0;
begin
MODULE port map(......count => counter.....); --this is an inout port
end structural;
我想实现一个计数器,它根据输入信号 signalIn
到 my_entity
的变化而递增,并将此计数器值传输到 MODULE
。
有没有办法在 my_entity
的行为架构中增加此 counter
信号?例如
architecture Behavioural of my_entity is
begin
process(signalIn)
begin
counter <= counter + 1;
end process;
end Behavioural;
当然,在此行为架构中,据报告 counter
未声明。我该如何解决这个问题?
您的问题在 counter
的一个体系结构中显示声明时没有显示信号 inSignal
的声明(这是一个信号,因为它显示在进程的敏感列表中)。您也不显示 MODULE
.
my_enity is
end entity;
architecture structural of my_entity is
signal counter: integer := 0;
begin
UNLABELLED_COMPONENT_INSTANTIATION: -- presuming count is declared mode in
MODULE port map(......count => counter.....); --this is an inout port
UNLABELLED_PROCESS:
process (inSignal)
begin
counter <= counter + 1;
end architecture structural;
您可以使用进程来操作计数器(请注意,它没有以易于合成的形式显示)或 不同[=21= 的单独组件实例] 实现计数器的实体架构对。
architecture pure_structural of my_entity is
signal counter: integer := 0;
begin
UNLABELLED_COMPONENT_INSTANTIATION: -- presuming count is declared mode in
MODULE port map(......count => counter.....); --this is an inout port
COUNTER_COMPONENT:
SOME_COUNTER port map (trigger => signalIn, count => counter);
-- where in this case count is mode out
end architecture pure_structural;