Xtensa 指令：L32R - 加载了哪个地址？
Xtensa instruction: L32R - which addres is loaded?
我正在尝试阅读一些 xtensa 汇编代码，但被 L32R 指令难住了：
例如给定以下行：
0000 2f04 <my_func>:
2f0c: ffef21 l32r a2, 2ec8
这个加载哪个地址？
Xtensa Instruction Set Architecture Reference Manual 手册第 382 页指出，对于 l32r，地址计算如下：
L32R forms a virtual address by adding the 16-bit one-extended constant value encoded
in the instruction word shifted left by two to the address of the L32R plus three with the
two least significant bits cleared. Therefore, the offset can always specify 32-bit aligned
addresses from -262141 to -4 bytes from the address of the L32R instruction. 32 bits
(four bytes) are read from the physical address.
所以继续上面的例子；常量操作：
ffef 16-bit constant
ffff ffef 16-bit constant one-extended
ffff ffbc shifted left by two
电脑操作：
0000 2f0c program counter
0000 2f0f pc +3
0000 0f0c masked bits 0 and 1
虚拟地址的计算：
ffff ffbc
+ 0000 2f0c
===========
1 0000 2ec8
因此丢弃超过 16 位的所有内容：2ec8
L32R 指令从指示的地址加载一个 32 位值。所以 "l32r a2, 2ec8" 将位于地址 0x2ec8 的 32 位值加载到寄存器 a2 中。您必须在反汇编中查看该位置。
我正在尝试阅读一些 xtensa 汇编代码，但被 L32R 指令难住了：
例如给定以下行：
0000 2f04 <my_func>:
2f0c: ffef21 l32r a2, 2ec8
这个加载哪个地址？
Xtensa Instruction Set Architecture Reference Manual 手册第 382 页指出，对于 l32r，地址计算如下：
L32R forms a virtual address by adding the 16-bit one-extended constant value encoded
in the instruction word shifted left by two to the address of the L32R plus three with the
two least significant bits cleared. Therefore, the offset can always specify 32-bit aligned
addresses from -262141 to -4 bytes from the address of the L32R instruction. 32 bits
(four bytes) are read from the physical address.
所以继续上面的例子；常量操作：
ffef 16-bit constant
ffff ffef 16-bit constant one-extended
ffff ffbc shifted left by two
电脑操作：
0000 2f0c program counter
0000 2f0f pc +3
0000 0f0c masked bits 0 and 1
虚拟地址的计算：
ffff ffbc
+ 0000 2f0c
===========
1 0000 2ec8
因此丢弃超过 16 位的所有内容：2ec8
L32R 指令从指示的地址加载一个 32 位值。所以 "l32r a2, 2ec8" 将位于地址 0x2ec8 的 32 位值加载到寄存器 a2 中。您必须在反汇编中查看该位置。