指令周期的取指阶段是如何工作的？
How do things work in the fetch phase of the instruction cycle?
有一点让我感到困惑，在计算机系统体系结构（Morris Mano）的第 5 章中，这本书使用了一个简单的微处理器，它具有以下指令周期：
例如LDA运算：
AR<---PC (T0)
IR<---M[AR] (T1)
PC<---PC+1 (T1)
解码 (T2)
DR<---M[AR] (T3)
AC<---DR (T4)
我很难理解这个周期以及为什么它不是这样的：
三月<--PC(T0)
MBR<---M(三月](T1)
解码(IR<---MBR)(T2)
MBR<--M(三月](T3)
AC<---MBR(T4)
我的问题是：
为什么书中没有使用MBR和MAR表示法，写操作需要读操作的结果，"read from memory"和"write to IR"操作如何同时完成？
没有MBR或MAR寄存器，设计中只有以下寄存器（忽略中断和IO功能）：
AR -- 地址寄存器；用于寻址内存
PC -- 程序计数器；正在执行的指令地址
DR -- 数据寄存器；数据的临时存储
AC -- 累加器；任何 ALU 运算的结果都在此寄存器中结束
IR -- 指令寄存器；当前指令操作码的存储
E -- ALU 操作的标志寄存器
SC -- 序列计数器；用于确定正在执行指令的哪一步
流经 LDA 指令例如：
T0: AR <- PC // Put the Program counter into the Address register so we can get the instruction; only the Address regsiter can access memory
T1: IR <- M[AR], PC <- PC + 1 // M[AR] means access memory (M) at address stored in AR ([AR]), and in this case put that value at address AR into the Instruction register; at the same time increment the Program counter which can be done in parallel as the increment can be done without using the bus
T2: Decode(IR); AR <- IR(0-11) // Now the instruction is decoded; during this time the address argument of the instruction is pass into the Address register
T3: DR <- M[AR] // Once weve determined in T2 that this is a LDA, we need to do the steps involved; the goal being to take the word from memory and get it into AC. To do this, we first need to read it out of memory, thus the M[AR], read memory at address AR (which is from the instruction became of the transfer we did in T2). We want to put it into AC, but since AC cannot be loaded from the bus directly, we need to put it somewhere else first, somewhere it can be then transferred to AC, thus put it in DR
T4: AC <- DR; SC <- 0 // Now that the data is in DR, we can move it via the ALU into AC; note that the ALU doesnt actually do any work on the data in the case of the LDA, it just passes the data through. Now that the instruction is done, reset the Sequence counter to 0
有一点让我感到困惑，在计算机系统体系结构（Morris Mano）的第 5 章中，这本书使用了一个简单的微处理器，它具有以下指令周期：
例如LDA运算：
AR<---PC (T0)
IR<---M[AR] (T1)
PC<---PC+1 (T1)
解码 (T2)
DR<---M[AR] (T3)
AC<---DR (T4)
我很难理解这个周期以及为什么它不是这样的：
三月<--PC(T0)
MBR<---M(三月](T1)
解码(IR<---MBR)(T2)
MBR<--M(三月](T3)
AC<---MBR(T4)
我的问题是：
为什么书中没有使用MBR和MAR表示法，写操作需要读操作的结果，"read from memory"和"write to IR"操作如何同时完成？
没有MBR或MAR寄存器，设计中只有以下寄存器（忽略中断和IO功能）：
AR -- 地址寄存器；用于寻址内存
PC -- 程序计数器；正在执行的指令地址
DR -- 数据寄存器；数据的临时存储
AC -- 累加器；任何 ALU 运算的结果都在此寄存器中结束
IR -- 指令寄存器；当前指令操作码的存储
E -- ALU 操作的标志寄存器
SC -- 序列计数器；用于确定正在执行指令的哪一步
流经 LDA 指令例如：
T0: AR <- PC // Put the Program counter into the Address register so we can get the instruction; only the Address regsiter can access memory
T1: IR <- M[AR], PC <- PC + 1 // M[AR] means access memory (M) at address stored in AR ([AR]), and in this case put that value at address AR into the Instruction register; at the same time increment the Program counter which can be done in parallel as the increment can be done without using the bus
T2: Decode(IR); AR <- IR(0-11) // Now the instruction is decoded; during this time the address argument of the instruction is pass into the Address register
T3: DR <- M[AR] // Once weve determined in T2 that this is a LDA, we need to do the steps involved; the goal being to take the word from memory and get it into AC. To do this, we first need to read it out of memory, thus the M[AR], read memory at address AR (which is from the instruction became of the transfer we did in T2). We want to put it into AC, but since AC cannot be loaded from the bus directly, we need to put it somewhere else first, somewhere it can be then transferred to AC, thus put it in DR
T4: AC <- DR; SC <- 0 // Now that the data is in DR, we can move it via the ALU into AC; note that the ALU doesnt actually do any work on the data in the case of the LDA, it just passes the data through. Now that the instruction is done, reset the Sequence counter to 0