用于 fpga 仿真的 Active-hdl 中的 MachX03 库错误

Question

编辑：我刚刚重新安装了lattice diamond和更新，Active-hdl是自动安装的，但是模拟仍然给我同样的错误。当我更改库 machXO3 时；使用 machXO3.all；到图书馆 machXO2；使用 machXO2.all；它编译..

我正在尝试为 OSCH 的简单实现编写一个测试平台，但我无法让测试平台工作。

几个月前我设法让它工作，但我丢失了我正在处理的文件。

这是我的 vhdl 代码：

library  ieee;
use  ieee.std_logic_1164.all;

-- For Main Clock --
library machXO3;
use machXO3.all;
--------------------

entity Clock is
     port (stdby : in std_logic;
           osc_int: out std_logic
           );
end Clock;

architecture Clock_behav of Clock is

    COMPONENT OSCH
    -- synthesis translate_off
        GENERIC (NOM_FREQ: string := "2.56");
    -- synthesis translate_on
        PORT (STDBY : IN std_logic;
              OSC : OUT std_logic
                );
    END COMPONENT;

begin

    Clock: OSCH
    -- synthesis translate_off
    GENERIC MAP( NOM_FREQ => "2.56" )
    -- synthesis translate_on
    PORT MAP (  STDBY => stdby,
                OSC => osc_int
    );

end Clock_behav;

这是testbench，大部分是lattice-diamond生成的我只加了stdby <= '0';

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY testbench IS
END testbench;

ARCHITECTURE behavior OF testbench IS 

    COMPONENT Clock
    PORT(
        stdby : IN std_logic;          
        osc_int : OUT std_logic
        );
    END COMPONENT;

    SIGNAL stdby :  std_logic;
    SIGNAL osc_int :  std_logic;

BEGIN

-- Please check and add your generic clause manually
    uut: Clock PORT MAP(
        stdby => stdby,
        osc_int => osc_int
    );
    stdby <= '0';

-- *** Test Bench - User Defined Section ***
   tb : PROCESS
   BEGIN
      --wait; -- will wait forever
   END PROCESS;
-- *** End Test Bench - User Defined Section ***

END;

Lattice-diamond 告诉我一切正常，但是当我运行 Active-hdl 中的所有内容进行模拟时，我得到这些错误：

# Error: COMP96_0059: Main.vhd : (5, 1): Library "machXO3" not found.
# Error: COMP96_0078: Main.vhd : (6, 5): Unknown identifier "machXO3".
# Compile Architecture "Clock_behav" of Entity "Clock"
# Error: COMP96_0056: Main.vhd : (15, 1): Cannot find referenced entity declaration "Clock".
# Compile failure 3 Errors 0 Warnings  Analysis time :  16.0 [ms]

Answer 1

看C:\lscc\diamond.10_x64\active-hdl\vlib\，好像没有machXO3库，但是有machxo、machxo2和machxo3l库。更改库 machXO3；使用 machXO3.all；到图书馆 machXO3l；使用 machXO3l.all；对测试台进行一些小的修改，一切似乎都很好。

新测试平台

    -- VHDL Test Bench Created from source file Clock.vhd -- Fri Feb 22 13:56:19 2019

    --
    -- Notes: 
    -- 1) This testbench template has been automatically generated using types
    -- std_logic and std_logic_vector for the ports of the unit under test.
    -- Lattice recommends that these types always be used for the top-level
    -- I/O of a design in order to guarantee that the testbench will bind
    -- correctly to the timing (post-route) simulation model.
    -- 2) To use this template as your testbench, change the filename to any
    -- name of your choice with the extension .vhd, and use the "source->import"
    -- menu in the ispLEVER Project Navigator to import the testbench.
    -- Then edit the user defined section below, adding code to generate the 
    -- stimulus for your design.
    -- 3) VHDL simulations will produce errors if there are Lattice FPGA library 
    -- elements in your design that require the instantiation of GSR, PUR, and
    -- TSALL and they are not present in the testbench. For more information see
    -- the How To section of online help.  
    --
    LIBRARY ieee;
    USE ieee.std_logic_1164.ALL;
    USE ieee.numeric_std.ALL;

    ENTITY testbench IS
    END testbench;

    ARCHITECTURE behavior OF testbench IS 

        COMPONENT Clock
        PORT(
            stdby : IN std_logic;          
            osc_int : OUT std_logic
            );
        END COMPONENT;

        SIGNAL stdby :  std_logic;
        SIGNAL osc_int :  std_logic;  
        constant PERIOD : time := 20 ns;

    BEGIN

    -- Please check and add your generic clause manually
        uut: Clock PORT MAP(
            stdby => stdby,
            osc_int => osc_int
        );


    -- *** Test Bench - User Defined Section ***
       tb : PROCESS
       BEGIN  
           stdby <= '0';  
           wait for PERIOD ;
          wait; -- will wait forever
       END PROCESS;
    -- *** End Test Bench - User Defined Section ***

    END;

用于 fpga 仿真的 Active-hdl 中的 MachX03 库错误

MachX03 library error in Active-hdl for fpga simulation

vhdl

lattice-diamond

active-hdl