Xilinx FFT v8.0 核心示例测试平台

Question

我正在尝试使用 Virtex 7 上的 Xilinx FFTv8.0 内核计算一系列 16 位输入值的 DFT 变换，但我在理解数据表时遇到了一些麻烦。

更具体地说，我使用的是标准的自动生成的测试平台（见下文），但输出始终为零。翻了很多遍datasheet和"Jim Wu's FPGA Blog" (http://myfpgablog.blogspot.de/2010/07/fft-results-from-matlab-fft-bit.html)，还是不明白怎么用。我想我被核心的倍数input/output搞糊涂了..

`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   14:25:20 05/14/2015
// Design Name:   fft_core
// Module Name:   C:/Users/Alberto/Documents/MEGA/Master II/Master Thesis/test_fft/fft_tb.v
// Project Name:  test_fft
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: fft_core
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module fft_tb;

    // Inputs
    reg aclk;
    reg s_axis_config_tvalid;
    reg s_axis_data_tvalid;
    reg s_axis_data_tlast;
    reg m_axis_data_tready;
    reg [7:0] s_axis_config_tdata;
    reg [31:0] s_axis_data_tdata;

    // Outputs
    wire s_axis_config_tready;
    wire s_axis_data_tready;
    wire m_axis_data_tvalid;
    wire m_axis_data_tlast;
    wire event_frame_started;
    wire event_tlast_unexpected;
    wire event_tlast_missing;
    wire event_status_channel_halt;
    wire event_data_in_channel_halt;
    wire event_data_out_channel_halt;
    wire [31:0] m_axis_data_tdata;

    // generate clk
    always #5 aclk =! aclk;

    // Instantiate the Unit Under Test (UUT)
    fft_core uut (
        .aclk(aclk), 
        .s_axis_config_tvalid(s_axis_config_tvalid), 
        .s_axis_data_tvalid(s_axis_data_tvalid), 
        .s_axis_data_tlast(s_axis_data_tlast), 
        .m_axis_data_tready(m_axis_data_tready), 
        .s_axis_config_tready(s_axis_config_tready), 
        .s_axis_data_tready(s_axis_data_tready), 
        .m_axis_data_tvalid(m_axis_data_tvalid), 
        .m_axis_data_tlast(m_axis_data_tlast), 
        .event_frame_started(event_frame_started), 
        .event_tlast_unexpected(event_tlast_unexpected), 
        .event_tlast_missing(event_tlast_missing), 
        .event_status_channel_halt(event_status_channel_halt), 
        .event_data_in_channel_halt(event_data_in_channel_halt), 
        .event_data_out_channel_halt(event_data_out_channel_halt), 
        .s_axis_config_tdata(s_axis_config_tdata), 
        .s_axis_data_tdata(s_axis_data_tdata), 
        .m_axis_data_tdata(m_axis_data_tdata)
    );

    initial begin
        // Initialize Inputs
        aclk = 0;
        s_axis_config_tvalid = 0;
        s_axis_data_tvalid = 0;
        s_axis_data_tlast = 0;
        m_axis_data_tready = 0;
        s_axis_config_tdata = 0;
        s_axis_data_tdata = 0;

        // Wait 100 ns for global reset to finish
        #150;

        s_axis_config_tvalid = 1;
        s_axis_data_tvalid = 1;
        //s_axis_data_tlast = 1;
        m_axis_data_tready = 1;
        s_axis_config_tdata = 1;
        s_axis_data_tdata = 1;

        // Add stimulus here

        // Some random inputs (just to understand how it works):
        s_axis_config_tdata = 8'b00000001; // FFT desired (and not IFFT)
        s_axis_data_tdata = 32'h00005678; // I have a real input signal, so the upper half (corresponding to the immaginary part) is zero
        #10;
        s_axis_config_tdata = 8'b00000001;
        s_axis_data_tdata = 32'h00001121;
        #10;
        s_axis_config_tdata = 8'b00000001;
        s_axis_data_tdata = 32'h00001516;
        #10;
        s_axis_config_tdata = 8'b00000001;
        s_axis_data_tdata = 32'h00001920;
        #10;
        s_axis_config_tdata = 8'b00000001;
        s_axis_data_tdata = 32'h00001121;
        #10;
        s_axis_config_tdata = 8'b00000001;
        s_axis_data_tdata = 32'h00001516;
        #10;
        s_axis_config_tdata = 8'b00000001;
        s_axis_data_tdata = 32'h00001920;
        #10;
        s_axis_config_tdata = 8'b00000001;
        s_axis_data_tdata = 32'h00001121;
        #10;
        s_axis_config_tdata = 8'b00000001;
        s_axis_data_tdata = 32'h00001516;
        #10;
        s_axis_config_tdata = 8'b00000001;
        s_axis_data_tdata = 32'h00001920;
        #10;
        s_axis_config_tdata = 8'b00000001;
        s_axis_data_tdata = 32'h00001121;
        #10;
        s_axis_config_tdata = 8'b00000001;
        s_axis_data_tdata = 32'h00001516;
        #10;
        s_axis_config_tdata = 8'b00000001;
        s_axis_data_tdata = 32'h00001920;
        #10;
        s_axis_config_tdata = 8'b00000001;
        s_axis_data_tdata = 32'h00001121;
        #10;
        s_axis_config_tdata = 8'b00000001;
        s_axis_data_tdata = 32'h00001516;
        #10;
        s_axis_config_tdata = 8'b00000001;
        s_axis_data_tdata = 32'h00001920;
        #10;


    end

endmodule

以下是我使用的波形图和核心配置的一些截图（我还没有权限直接post）： https://www.dropbox.com/s/0ejccc4dm6zdw7h/FFT.zip?dl=0

有人有解释或工作测试平台（可能用 Verilog 编写）处理这个 ip 核的数据吗？

提前谢谢你

编辑：

对于post优先级，完整代码可用here; details and explanations can be found in the paper。

Answer 1

我终于解决了我的问题。核心在传送数据之前有巨大的延迟（几个我们）。所以如果其他人有同样的问题，不要犹豫，大幅增加模拟时间，它可能会解决你的问题。

Xilinx FFT v8.0 核心示例测试平台

Xilinx FFT v8.0 core example testbench

fft

xilinx

编辑：