我已经用 VHDL 为我的项目编写代码，但在使用信号时出现错误

Question

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity keygeneration is
    Port ( key : in  STD_LOGIC_VECTOR (127 downto 0);
           rc : in  STD_LOGIC_VECTOR (3 downto 0);
           keyout : out  STD_LOGIC_VECTOR (127 downto 0));
end keygeneration;

architecture Behavioral of keygeneration is

component sbox is
     port(a: in std_logic_vector(7 downto 0);
          y: out std_logic_vector(7 downto 0));
end component;
component RCON is
 Port ( rc : in  STD_LOGIC_VECTOR (3 downto 0);
            rout : out  STD_LOGIC_VECTOR (31 downto 0));
end component;
signal w0,w1,w2,w3,tem: STD_LOGIC_VECTOR (31 downto 0);
signal rout1: STD_LOGIC_VECTOR (31 downto 0);

begin
-- 52nd line below
w0<=key[127 downto 96];
w1<=key[95 downto 64];
w2<=key[63 downto 32];
w3<=key[31 downto 0];

t1: sbox port map(w3[23 downto 16],tem[31 downto 0]);
t2: sbox port map(w3[15 downto 8],tem[23 downto 16]);
t3: sbox port map(w3[7 downto 0],tem[15 downto 8]);
t4: sbox port map(w3[31 downto 24],tem[7 downto 0]);

r1: RCON port map(rc[3 downto 0],rout1[31 downto 0]);

keyout[127 downto 96]<=w0^tem^rout1;
keyout[95 downto 64]<=w0^tem^rout1^w1;
keyout[63 downto 32]<=w0^tem^rout1^w1^w2;
keyout[31 downto 0]<=w0^tem^rout1^w1^w2^w3;

end Behavioral;

发现的错误是

ERROR:HDLParsers:164 - "D:/Files/newpro/keygeneration.vhd" Line 52. parse error, unexpected INTEGER_LITERAL, expecting RETURN or IDENTIFIER or RSQBRACK.

我已经显示了代码中的第 52 行。我对第 52 行的所有赋值语句都有同样的错误。请帮忙。提前致谢

Answer 1

2 个错误：

VHDL 不使用 [] 来索引数组（尽管它们用于 signatures）。使用 () 代替数组索引。

VHDL 中没有 ^ 运算符。请改用 xor。

Answer 2

你不是这个意思:

w0<=key[127 downto 96];

你是这个意思：

w0<=key(127 downto 96);

我已经用 VHDL 为我的项目编写代码，但在使用信号时出现错误

I have written code for my project in VHDL, but im getting an error while using signal

fpga

vhdl