vhdl中的乘加运算符

Question

vhdl 中是否有定义 * 和 + 运算符的库？我需要乘法和加法超过 128 位数字。如果是，它们可以合成吗？请帮忙。

Answer 1

是的。例如：

library ieee;
use ieee.numeric_std.all;

...

  signal a : signed(31 downto 0); -- 32-bit signed value
  signal b : signed(7 downto 0);  -- 8-bit signed value
  signal c : signed(39 downto 0); -- 40-bit signed value

...

  c <= a * b;  -- Note 'c' is as wide as the sum of a's length and b's length

numeric_std 包定义了 unsigned 和 signed 类型。它还为这些定义了运算符。请注意，将 signed 和 unsigned 与 integers 和 naturals 混合也是允许的（受一些限制）。例如：

  signal a : signed(31 downto 0);
  signal b : signed(31 downto 0);

...

  b <= a * 17;  -- Multiply by a constant

在这些情况下必须小心，以确保不会发生溢出。

并且这些是可综合的（我们在实际设计中一直使用它们）。

Answer 2

对于@PlayDough 的解决方案，我建议使用 VHDL 属性来定义结果的矢量长度。

   library ieee;
   use ieee.numeric_std.all;

...

  signal a : signed(31 downto 0); -- 32-bit signed value
  signal b : signed(7 downto 0);  -- 8-bit signed value
  signal c : signed(a'length+b'length-1 downto 0); -- 40-bit signed value
  signal d : signed(a'range);

...

  c <= a * b;  -- Note 'c' is as wide as the sum of a's length and b's length
  d <= a + b;  -- Note 'd' is as wide as the widest term in addition

使用整数常量很棘手，因为结果的向量长度未定义。你应该在算术运算之前将它们转换为 signed/unsigned 向量。

  signal a : signed(31 downto 0);
  signal b : signed(a'length+5 downto 0);

...

  b <= a * to_signed(17, 6);  -- Multiply by a constant

vhdl中的乘加运算符

Multiply and add operators in vhdl

fpga

vhdl