在 for-generate 语句中为信号赋值

Question

我不明白为什么在下面的例子中 "sig2" 的信号分配不会成功，而 "sig1" 却可以。随着时钟上升沿 "sig2" 变为 'X'!

这是什么原因？

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.all;

entity Test_tb is
end entity Test_tb;

architecture Structural of Test_tb is

    signal sig1 : std_logic_vector (3 downto 0) := (others => '0');
    signal sig2 : std_logic_vector (7 downto 0) := (others => '0');
    signal clk : std_logic := '0';

begin
    clk_generate: process is
    begin
        wait for 5 ns;
        clk <= not clk;        
    end process clk_generate;

    gen_label : for gen_indx in 0 to 3 generate
    begin
        process (clk) is 
        begin
            if clk = '1' and clk'event then
                sig1 (gen_indx) <= '1';
                for loop_indx in 0 to 1 loop
                    sig2 (gen_indx * 2 + loop_indx) <= '1';
                end loop;
            end if; 
        end process;
    end generate gen_label;

end architecture Structural;

Answer 1

这是因为，当在 for 循环内分配信号时，假定驱动程序会影响数组（或记录）的所有元素。这是因为它无法在精化时计算出 for 循环的边界，因为它是一个运行时间概念。这不同于生成循环，在生成循环中可以在详细说明时推导出边界。

因此您需要从进程内部删除 for 循环，或者创建一个本地信号到分配给外部 sig2 的生成循环。例如：

gen_label : for gen_indx in 0 to 3 generate
  signal local_sig  : std_logic_vector(1 downto 0);
begin
    process (clk) is 
    begin
        if clk = '1' and clk'event then
            sig1 (gen_indx) <= '1';
            for loop_indx in 0 to 1 loop
                local_sig(loop_indx) <= '1';
            end loop;
        end if; 
    end process;

    sig2(gen_indx*2+1 downto gen_indx*2)  <= local_sig;
end generate gen_label;

在 for-generate 语句中为信号赋值

Assigning values to signals within for-generate statements

vhdl

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generate