信号电流无法合成,同步不良说明
Signal current cannot be synthesized, bad synchronous description
我在 Xillinx 中综合此代码时出错。这个错误是:
Analyzing Entity in library (Architecture ).
ERROR:Xst:827 - "C:/Xilinx92i/Parking/Parking.vhd" line 43: Signal current cannot be synthesized, bad synchronous description.
entity Parking is port(
A, B ,reset: in std_logic;
Capacity : out std_logic_vector(7 downto 0));
end Parking;
architecture Behavioral of Parking is
type state is (NoChange, Aseen, Bseen, ABseen, BAseen, Input, Output, Din, Dout);
signal current, nxt : state ;
signal counter : std_logic_vector (7 downto 0) := "00000000";
begin
p1: process(A, B, reset)
begin
if reset = '1' then
current <= Nochange;
end if;
if(A'event and A='1') then
current <= nxt;
end if;
if(A'event and A='0') then
current <= nxt;
end if;
if(B'event and B='1') then
current <= nxt;
end if;
if(B'event and B='0') then
current <= nxt;
end if;
end process;
p2: process(current, A, B)
begin
case current is
when Aseen =>
if B='1' then
nxt <= ABseen;
else
nxt <= NoChange;
end if;
when others =>
nxt <= Nochange;
end case;
end process;
Capacity <= counter;
end Behavioral;
错误'bad synchronous description'通常意味着您描述了硬件中不存在的寄存器(时钟元件)。
对于您的代码,您有:
if(A'event and A='1') then
current <= nxt;
end if;
if(A'event and A='0') then
current <= nxt;
end if;
-- etc
在一个进程中。同步可综合进程通常只有一个时钟,因为在像 FPGA 这样的真实硅器件中没有任何元件可以响应两个不同时钟上的事件。与您尝试实施的流程类似的流程通常看起来更像这样:
process (clk)
begin
if (rising_edge(clk)) then
if (a = '1') then
current <= nxt;
elsif (a = '0') then
current <= nxt;
end if;
end if;
end process;
以这种方式实施它需要您具备:
- 您系统中的时钟
- 相对于此时钟满足setup/hold次的输入
旁注
如果您没有一个有意义的进程名称,则根本不必给它命名。 process (clk)
与 p1 : process(clk)
一样有效。
我在 Xillinx 中综合此代码时出错。这个错误是:
Analyzing Entity in library (Architecture ).
ERROR:Xst:827 - "C:/Xilinx92i/Parking/Parking.vhd" line 43: Signal current cannot be synthesized, bad synchronous description.
entity Parking is port(
A, B ,reset: in std_logic;
Capacity : out std_logic_vector(7 downto 0));
end Parking;
architecture Behavioral of Parking is
type state is (NoChange, Aseen, Bseen, ABseen, BAseen, Input, Output, Din, Dout);
signal current, nxt : state ;
signal counter : std_logic_vector (7 downto 0) := "00000000";
begin
p1: process(A, B, reset)
begin
if reset = '1' then
current <= Nochange;
end if;
if(A'event and A='1') then
current <= nxt;
end if;
if(A'event and A='0') then
current <= nxt;
end if;
if(B'event and B='1') then
current <= nxt;
end if;
if(B'event and B='0') then
current <= nxt;
end if;
end process;
p2: process(current, A, B)
begin
case current is
when Aseen =>
if B='1' then
nxt <= ABseen;
else
nxt <= NoChange;
end if;
when others =>
nxt <= Nochange;
end case;
end process;
Capacity <= counter;
end Behavioral;
错误'bad synchronous description'通常意味着您描述了硬件中不存在的寄存器(时钟元件)。
对于您的代码,您有:
if(A'event and A='1') then
current <= nxt;
end if;
if(A'event and A='0') then
current <= nxt;
end if;
-- etc
在一个进程中。同步可综合进程通常只有一个时钟,因为在像 FPGA 这样的真实硅器件中没有任何元件可以响应两个不同时钟上的事件。与您尝试实施的流程类似的流程通常看起来更像这样:
process (clk)
begin
if (rising_edge(clk)) then
if (a = '1') then
current <= nxt;
elsif (a = '0') then
current <= nxt;
end if;
end if;
end process;
以这种方式实施它需要您具备:
- 您系统中的时钟
- 相对于此时钟满足setup/hold次的输入
旁注
如果您没有一个有意义的进程名称,则根本不必给它命名。 process (clk)
与 p1 : process(clk)
一样有效。