如何在 IBM (HLASM) 中使用显式寻址
How to use explicit addressing in IBM (HLASM)
一直在网上找关于显式寻址的资料，但是没有也有，解释很模糊。我希望有人能详细解释我，并在可能的情况下举例说明。
我想知道，应该使用什么寄存器作为索引，基数，位移值应该是什么
示例 8(,4) 或 5(0,5) 或 6(7)
这取决于正在执行的指令。请参阅来自 IBM 的参考资料以帮助整理详细信息。作为一个老 Z 表演者，当人们问起关于表演的问题时，答案几乎总是“视情况而定”
看到这个article
Registers that are not explicitly coded in symbolic assembler language
representation of machine instructions, but are nevertheless used by
assembled machine instructions, are divided into two categories: Base
registers that are implicit in the symbolic addresses specified. (See
Addresses.) The registers can be identified by examining the object
code or the USING instructions that assign base registers for the
source module.
Registers that are used by machine instructions, but do
not appear in assembled object code.
For double shift and fullword multiply and divide instructions, the odd-numbered register, whose number is one greater than the even-numbered register specified as the first operand.
For Move Long and Compare Logical Long instructions,
the odd-numbered registers, whose number is one greater than
even-numbered registers specified in the two operands.
For Branch on Index High (BXH) and the Branch on Index Low or Equal (BXLE)
instructions, if the register specified for the second operand is an
even-numbered register, the next higher odd-numbered register is used
to contain the value to be used for comparison.
For Load Multiple (LM, LAM) and Store Multiple (STM, STAM) instructions, the registers that lie between the registers specified in the first two operands.
For extended-precision floating point instructions, the second register of
the register pair.
For Compare and Form Codeword (CFC) instruction, registers 1, 2, and 3 are used. >
For Translate and Test (TRT) instruction, registers 1 and 2 are used. For Update Tree (UPT) instruction, registers 0-5 are used.
For Edit and Mark (EDMK) instruction, register 1 is used. For certain control instructions, one or more of registers 0-4 and register 14 are used. See "Control
Instructions" in the applicable z/Architecture Principles of Operation
manual.
For certain input and output instructions, either or both registers 1 and 2 are used. See "Input/Output Instructions" in the applicable z/Architecture Principles of Operation manual.
On a processor with a vector facility:
For instructions that manipulate long floating-point data in vector registers, the odd-numbered vector
registers, whose number is one greater than the even-numbered vector
registers specified in each operand.
For instructions that manipulate
64 bit signed binary data in vector registers, the odd-numbered vector
registers, whose number is one greater than the even-numbered vector
registers specified in each operand.
一直在网上找关于显式寻址的资料，但是没有也有，解释很模糊。我希望有人能详细解释我，并在可能的情况下举例说明。 我想知道，应该使用什么寄存器作为索引，基数，位移值应该是什么
示例 8(,4) 或 5(0,5) 或 6(7)
这取决于正在执行的指令。请参阅来自 IBM 的参考资料以帮助整理详细信息。作为一个老 Z 表演者，当人们问起关于表演的问题时，答案几乎总是“视情况而定”
看到这个article
Registers that are not explicitly coded in symbolic assembler language representation of machine instructions, but are nevertheless used by assembled machine instructions, are divided into two categories: Base registers that are implicit in the symbolic addresses specified. (See Addresses.) The registers can be identified by examining the object code or the USING instructions that assign base registers for the source module.
Registers that are used by machine instructions, but do not appear in assembled object code. For double shift and fullword multiply and divide instructions, the odd-numbered register, whose number is one greater than the even-numbered register specified as the first operand.
For Move Long and Compare Logical Long instructions, the odd-numbered registers, whose number is one greater than even-numbered registers specified in the two operands.
For Branch on Index High (BXH) and the Branch on Index Low or Equal (BXLE) instructions, if the register specified for the second operand is an even-numbered register, the next higher odd-numbered register is used to contain the value to be used for comparison.
For Load Multiple (LM, LAM) and Store Multiple (STM, STAM) instructions, the registers that lie between the registers specified in the first two operands.
For extended-precision floating point instructions, the second register of the register pair.
For Compare and Form Codeword (CFC) instruction, registers 1, 2, and 3 are used. > For Translate and Test (TRT) instruction, registers 1 and 2 are used. For Update Tree (UPT) instruction, registers 0-5 are used.
For Edit and Mark (EDMK) instruction, register 1 is used. For certain control instructions, one or more of registers 0-4 and register 14 are used. See "Control Instructions" in the applicable z/Architecture Principles of Operation manual.
For certain input and output instructions, either or both registers 1 and 2 are used. See "Input/Output Instructions" in the applicable z/Architecture Principles of Operation manual. On a processor with a vector facility:
For instructions that manipulate long floating-point data in vector registers, the odd-numbered vector registers, whose number is one greater than the even-numbered vector registers specified in each operand.
For instructions that manipulate 64 bit signed binary data in vector registers, the odd-numbered vector registers, whose number is one greater than the even-numbered vector registers specified in each operand.