向量中每个位的 VHDL 映射

Question

为向量中的每一位执行端口映射的最佳方法是什么？假设我有一个表示一系列按钮的矢量，并希望使用反跳模块对每个按钮进行反跳，我应该怎么做？

目前我有以下这些，但我相信应该有更好的方法

entity ButtonDebouncer is
    Port (
        clock : in std_logic;
        buttons : in std_logic_vector(0 to 5);
        --{ more stuff }
    );
end ButtonDebouncer;

architecture Behavioral of ButtonDebouncer is
    signal bufferedButtons : std_logic_vector(0 to 5) := (others => '0');
begin
    c1: entity debounce port map (Clock, buttons(0), bufferedButtons(0));
    c2: entity debounce port map (Clock, buttons(1), bufferedButtons(1));
    c3: entity debounce port map (Clock, buttons(2), bufferedButtons(2));
    c4: entity debounce port map (Clock, buttons(3), bufferedButtons(3));
    c5: entity debounce port map (Clock, buttons(4), bufferedButtons(4));
    c6: entity debounce port map (Clock, buttons(5), bufferedButtons(5));

    --{ Do stuff with debounced buttons }
end Behavioral;

Answer 1

For generate 在这里是一个很好的候选结构。

entity ButtonDebouncer is
    Port (
        clock : in std_logic;
        buttons : in std_logic_vector(0 to 5);
        --{ more stuff }
    );
end ButtonDebouncer;

architecture Behavioral of ButtonDebouncer is
    signal bufferedButtons : std_logic_vector(0 to 5) := (others => '0');
begin
    debouncers: for i in 0 to 5 generate
        c1: entity debounce port map (Clock, buttons(i), bufferedButtons(i));
    end generate;
    --{ Do stuff with debounced buttons }
end Behavioral;

Answer 2

Travis 的解决方案是一个很好的起点。

我会更进一步，为多个位实现一个 debounce 模块。所以你可以将整个按钮向量传递给这个模块。

entity debounce is
  generic (
    BITS   : POSITIVE
  );
  port (
    Clock   : STD_LOGIC;
    Input   : STD_LOGIC_VECTOR(BITS - 1 downto 0);
    Output  : STD_LOGIC_VECTOR(BITS - 1 downto 0)
  )
end entity;

architecture rtl of debounce is
  -- define 'global' signals here (per instance)
begin
  genDebounce : for i in 0 to BITS - 1 generate
    -- define 'local' signals here (per debounce circuit)
  begin
    -- debounce circuit
  end generate;
end architecture;

用法：

debButtons : entity work.debounce
  generic map (
    BITS    => buttons'length
  )
  port map (
    Clock   => Clock,
    Input   => Buttons,
    Output  => bufferedButtons
  );

向量中每个位的 VHDL 映射

VHDL map for each bit in a vector

loops

dictionary

entity

port

vhdl