Verilog 计数器不会触发不同的时钟信号

Question

我正在尝试编写一个计数器，它只跟踪时钟的上升沿并在它上升时递增一个变量。需要注意的是该电路必须在不同的时钟源之间切换。计数器和时钟多路复用器的功能与仿真中的默认时钟一样，但计数器似乎没有看到第二个时钟信号的上升沿。我自己测试了多路复用器，它正确地传递了时钟信号。有什么想法吗？

顶层模块：

module hw1_top(reset, updown, inp, clkSwitch, Clk100MHz, testClock2, out);
input reset, updown, Clk100MHz, testClock2;
input [15:0] inp;
input [3:0] clkSwitch;

output [15:0] out;

wire muxtoclk;

ClockMux mux(
    .c1(Clk100MHz),
    .c2(testClock2),
    .switch(clkSwitch),
    .cOut(muxtoclk)
);

UDCounter counter(
    .RST(reset),
    .UD(updown),
    .INP(inp),
    .CLK(muxtoclk),
    .OUT(out)
);  
endmodule

专柜：

module UDCounter(RST, UD, INP, CLK, OUT);
input RST, UD, CLK; //1 bit inputs
input [15:0] INP; //16 bit input

output reg [15:0] OUT; //16 bit output, must be reg for sequential

initial
    OUT <= INP; //when we start, counter initializes to whatever the input is

always@(posedge CLK or posedge RST) //on every positive edge of the clock cycle, or if reset is triggered...
    if(RST == 1'b1) //if reset is high, set counter back to the initial input
        OUT <= INP;
    else //if reset isn't triggered...
        if(UD == 1'b0) //if up/down is in up position, count up
            begin
                OUT <= OUT + 1;
            end
        else //if in down, count down
            begin
                OUT <= OUT -1;
            end
endmodule

多路复用器：

module ClockMux(c1,c2,switch,cOut);switch,cOut);
input c1,c2;
input [3:0] switch;

output reg cOut;

always@(switch,c1,c2) //updates whenever the switch or clock changes
    case(switch)
        4'b0000: cOut <= c1;
        4'b0001: cOut <= c2;
    endcase
 endmodule

顶级测试平台和波形：

module hw1_top_tb();
reg reset, updown, Clk100MHz, testClock2;
reg [15:0] inp;

wire [15:0] out;
reg [3:0] switchValue;

hw1_top topmod(
    .reset(reset),
    .updown(updown),
    .inp(inp),
    .clkSwitch(switchValue),
    .Clk100MHz(Clk100MHz),
    .out(out)
);

initial Clk100MHz = 0;
always #5 Clk100MHz = ~Clk100MHz;

initial testClock2 = 0;
always #3 testClock2 = ~testClock2;

initial begin
    reset = 0; updown = 0; inp = 16'b0; switchValue = 4'b0000; 
    #10;
    reset = 1; updown = 0; inp = 16'b0; switchValue = 4'b0000; 
    #10; //toggles the reset briefly to clear dc's

    reset = 0; updown = 0; inp = 16'b0; switchValue = 4'b0000;
    #40;
    reset = 1; updown = 0; inp = 16'b0; switchValue = 4'b0001; //counter is not listening here
    #10;
    reset = 0; updown = 0; inp = 16'b0; switchValue = 4'b0001; //counter is not listening here
    #23;
    reset = 1; updown = 0; inp = 16'b0; switchValue = 4'b0000; //when we switch back, it's doing great
    #13;
    reset = 0; updown = 0; inp = 16'b0; switchValue = 4'b0000;
    #23;
    $finish;
end
 endmodule

Answer 1

您从未在 hw1_top 的实例化 topmod 中连接 testClock2：

hw1_top topmod(
    .reset(reset),
    .updown(updown),
    .inp(inp),
    .clkSwitch(switchValue),
    .Clk100MHz(Clk100MHz),
    .testClock2(testClock2), // this is missing
    .out(out)
);

Verilog 计数器不会触发不同的时钟信号

Verilog counter does not trigger for different clock signals

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