Verilog：define_state.h 处的声明错误：标识符已在当前范围内声明
Verilog: Declaration error at define_state.h: identifier is already declared in the present scope
我现在要做的就是克服这个错误，这样我就可以开始测试代码了，它是用于硬件图像压缩器的。
主 .v 文件：
`timescale 1ns/100ps
`ifndef DISABLE_DEFAULT_NET
`default_nettype none
`endif
`include "define_state.h"
// This is the top module
// It connects the UART, SRAM and VGA together.
// It gives access to the SRAM for UART and VGA
module experiment4a (
/////// board clocks ////////////
input logic CLOCK_50_I, // 50 MHz clock
/////// pushbuttons/switches ////////////
input logic[3:0] PUSH_BUTTON_I, // pushbuttons
input logic[17:0] SWITCH_I, // toggle switches
/////// 7 segment displays/LEDs ////////////
output logic[6:0] SEVEN_SEGMENT_N_O[7:0], // 8 seven segment displays
output logic[8:0] LED_GREEN_O, // 9 green LEDs
/////// VGA interface ////////////
output logic VGA_CLOCK_O, // VGA clock
output logic VGA_HSYNC_O, // VGA H_SYNC
output logic VGA_VSYNC_O, // VGA V_SYNC
output logic VGA_BLANK_O, // VGA BLANK
output logic VGA_SYNC_O, // VGA SYNC
output logic[7:0] VGA_RED_O, // VGA red
output logic[7:0] VGA_GREEN_O, // VGA green
output logic[7:0] VGA_BLUE_O, // VGA blue
/////// SRAM Interface ////////////
inout wire[15:0] SRAM_DATA_IO, // SRAM data bus 16 bits
output logic[19:0] SRAM_ADDRESS_O, // SRAM address bus 18 bits
output logic SRAM_UB_N_O, // SRAM high-byte data mask
output logic SRAM_LB_N_O, // SRAM low-byte data mask
output logic SRAM_WE_N_O, // SRAM write enable
output logic SRAM_CE_N_O, // SRAM chip enable
output logic SRAM_OE_N_O, // SRAM output logic enable
/////// UART ////////////
input logic UART_RX_I, // UART receive signal
output logic UART_TX_O // UART transmit signal
);
logic resetn;
top_state_type top_state;
state_type state;
// For Push button
logic [3:0] PB_pushed;
// For VGA SRAM interface
logic VGA_enable;
logic [17:0] VGA_base_address;
logic [17:0] VGA_SRAM_address;
// For SRAM
logic [17:0] SRAM_address;
logic [15:0] SRAM_write_data;
logic SRAM_we_n;
logic [15:0] SRAM_read_data;
logic SRAM_ready;
//For Milestone 1
parameter Y_offset = 0;
parameter U_offset = 38400;
parameter V_offset = 57600;
parameter RGB_offset = 146944;
logic [17:0] y_loc, uv_loc, rgb_loc;
logic [15:0] red, green, blue, r_hold, g_hold, b_hold;
logic [15:0] y, y_hold, u_prime, u_hold, v_prime, v_hold;
logic [7:0] u_comp [5:0];
logic [7:0] v_comp [5:0];
logic u_v_toggle;
logic lead_in;
logic [7:0] mult_1, mult_2, mult_3;
// For UART SRAM interface
logic UART_rx_enable;
logic UART_rx_initialize;
logic [17:0] UART_SRAM_address;
logic [15:0] UART_SRAM_write_data;
logic UART_SRAM_we_n;
logic [25:0] UART_timer;
logic [6:0] value_7_segment [7:0];
// For error detection in UART
logic [3:0] Frame_error;
// For disabling UART transmit
assign UART_TX_O = 1'b1;
assign resetn = ~SWITCH_I[17] && SRAM_ready;
// Push Button unit
PB_Controller PB_unit (
.Clock_50(CLOCK_50_I),
.Resetn(resetn),
.PB_signal(PUSH_BUTTON_I),
.PB_pushed(PB_pushed)
);
// VGA SRAM interface
logic [9:0] VGA_RED_O_long, VGA_GREEN_O_long, VGA_BLUE_O_long;
VGA_SRAM_interface VGA_unit (
.Clock(CLOCK_50_I),
.Resetn(resetn),
.VGA_enable(VGA_enable),
// For accessing SRAM
.SRAM_base_address(VGA_base_address),
.SRAM_address(VGA_SRAM_address),
.SRAM_read_data(SRAM_read_data),
// To VGA pins
.VGA_CLOCK_O(VGA_CLOCK_O),
.VGA_HSYNC_O(VGA_HSYNC_O),
.VGA_VSYNC_O(VGA_VSYNC_O),
.VGA_BLANK_O(VGA_BLANK_O),
.VGA_SYNC_O(VGA_SYNC_O),
.VGA_RED_O(VGA_RED_O_long),
.VGA_GREEN_O(VGA_GREEN_O_long),
.VGA_BLUE_O(VGA_BLUE_O_long)
);
assign VGA_RED_O = VGA_RED_O_long[9:2];
assign VGA_GREEN_O = VGA_GREEN_O_long[9:2];
assign VGA_BLUE_O = VGA_BLUE_O_long[9:2];
// UART SRAM interface
UART_SRAM_interface UART_unit(
.Clock(CLOCK_50_I),
.Resetn(resetn),
.UART_RX_I(UART_RX_I),
.Initialize(UART_rx_initialize),
.Enable(UART_rx_enable),
// For accessing SRAM
.SRAM_address(UART_SRAM_address),
.SRAM_write_data(UART_SRAM_write_data),
.SRAM_we_n(UART_SRAM_we_n),
.Frame_error(Frame_error)
);
// SRAM unit
SRAM_Controller SRAM_unit (
.Clock_50(CLOCK_50_I),
.Resetn(~SWITCH_I[17]),
.SRAM_address(SRAM_address),
.SRAM_write_data(SRAM_write_data),
.SRAM_we_n(SRAM_we_n),
.SRAM_read_data(SRAM_read_data),
.SRAM_ready(SRAM_ready),
// To the SRAM pins
.SRAM_DATA_IO(SRAM_DATA_IO),
.SRAM_ADDRESS_O(SRAM_ADDRESS_O[17:0]),
.SRAM_UB_N_O(SRAM_UB_N_O),
.SRAM_LB_N_O(SRAM_LB_N_O),
.SRAM_WE_N_O(SRAM_WE_N_O),
.SRAM_CE_N_O(SRAM_CE_N_O),
.SRAM_OE_N_O(SRAM_OE_N_O)
);
assign SRAM_ADDRESS_O[19:18] = 2'b00;
always @(posedge CLOCK_50_I or negedge resetn) begin
if (~resetn) begin
top_state <= S_IDLE;
UART_rx_initialize <= 1'b0;
UART_rx_enable <= 1'b0;
UART_timer <= 26'd0;
VGA_enable <= 1'b1;
end else begin
UART_rx_initialize <= 1'b0;
UART_rx_enable <= 1'b0;
// Timer for timeout on UART
// This counter reset itself every time a new data is received on UART
if (UART_rx_initialize | ~UART_SRAM_we_n) UART_timer <= 26'd0;
else UART_timer <= UART_timer + 26'd1;
case (top_state)
S_IDLE: begin
VGA_enable <= 1'b1;
if (~UART_RX_I | PB_pushed[0]) begin
// UART detected a signal, or PB0 is pressed
UART_rx_initialize <= 1'b1;
VGA_enable <= 1'b0;
top_state <= S_ENABLE_UART_RX;
end
end
S_ENABLE_UART_RX: begin
// Enable the UART receiver
UART_rx_enable <= 1'b1;
top_state <= S_WAIT_UART_RX;
end
S_WAIT_UART_RX: begin
if ((UART_timer == 26'd49999999) && (UART_SRAM_address != 18'h00000)) begin
// Timeout for 1 sec on UART for detecting if file transmission is finished
UART_rx_initialize <= 1'b1;
VGA_enable <= 1'b1;
top_state <= S_IDLE;
end
end
default: top_state <= S_IDLE;
endcase
end
end
assign VGA_base_address = 18'd0;
// Give access to SRAM for UART and VGA at appropriate time
assign SRAM_address = ((top_state == S_ENABLE_UART_RX) | (top_state == S_WAIT_UART_RX))
? UART_SRAM_address
: VGA_SRAM_address;
assign SRAM_write_data = UART_SRAM_write_data;
assign SRAM_we_n = ((top_state == S_ENABLE_UART_RX) | (top_state == S_WAIT_UART_RX))
? UART_SRAM_we_n
: 1'b1;
//Milestone 1
always_ff @ (posedge CLOCK_50_I or negedge resetn) begin
if (resetn == 1'b0) begin
SRAM_we_n <= 1'b1;
SRAM_write_data <= 16'd0;
SRAM_address <= 18'd0;
red = 16'd0;
green = 16'd0;
blue = 16'd0;
r_hold = 16'd0;
g_hold = 16'd0;
b_hold = 16'd0;
y = 16'd0;
y_hold = 16'd0;
u_prime = 16'd0;
u_hold = 16'd0;
u_comp [0] = 8'd0;
u_comp [1] = 8'd0;
u_comp [2] = 8'd0;
u_comp [3] = 8'd0;
u_comp [4] = 8'd0;
u_comp [5] = 8'd0;
v_prime = 16'd0;
v_hold = 16'd0;
v_comp [0] = 8'd0;
v_comp [1] = 8'd0;
v_comp [2] = 8'd0;
v_comp [3] = 8'd0;
v_comp [4] = 8'd0;
v_comp [5] = 8'd0;
u_v_toggle = 8'd0;
lead_in = 1'b1;
state <= S_IDLE;
end else begin
case (state)
S_IDLE: begin
red = 16'd0;
green = 16'd0;
blue = 16'd0;
r_hold = 16'd0;
g_hold = 16'd0;
b_hold = 16'd0;
y = 16'd0;
y_hold = 16'd0;
u_prime = 16'd0;
u_hold = 16'd0;
u_comp [0] = 8'd0;
u_comp [1] = 8'd0;
u_comp [2] = 8'd0;
u_comp [3] = 8'd0;
u_comp [4] = 8'd0;
u_comp [5] = 8'd0;
v_prime = 16'd0;
v_hold = 16'd0;
v_comp [0] = 8'd0;
v_comp [1] = 8'd0;
v_comp [2] = 8'd0;
v_comp [3] = 8'd0;
v_comp [4] = 8'd0;
v_comp [5] = 8'd0;
u_v_toggle = 8'd0;
SRAM_address <= U_offset;
uv_loc <= 18'd0;
y_loc <= 18'd0;
rgb_loc <= 18'd0;
SRAM_we_n <= 1'b0;
lead_in <=1'b1;
state <= S_LEAD_IN_1_U;
end
S_LEAD_IN_1_U: begin
u_hold <= SRAM_read_data;
u_comp [5] <=u_hold[15:8];
u_comp [4] <=u_hold[15:8];
u_comp [3] <=u_hold[15:8];
u_comp [2] <=u_hold[7:0];
SRAM_address <= SRAM_address + 18'd1;
uv_loc <= uv_loc + 18'd1;
state<= S_LEAD_IN_2_U;
end
S_LEAD_IN_2_U: begin
u_hold <= SRAM_read_data;
u_comp [1] <=u_hold[15:8];
u_comp [0] <=u_hold[7:0];
SRAM_address <= V_offset;
state<= S_LEAD_IN_3_V;
end
S_LEAD_IN_3_V: begin
v_hold <= SRAM_read_data;
v_comp [5] <=u_hold[15:8];
v_comp [4] <=u_hold[15:8];
v_comp [3] <=u_hold[15:8];
v_comp [2] <=u_hold[7:0];
SRAM_address <= SRAM_address + 18'd1;
state<= S_LEAD_IN_4_V;
end
S_LEAD_IN_4_V: begin
v_hold <= SRAM_read_data;
v_comp [1] <=u_hold[15:8];
v_comp [0] <=u_hold[7:0];
SRAM_address <= Y_offset;
state<= S_LEAD_IN_Y;
end
S_LEAD_IN_Y: begin
y = SRAM_read_data;
u_prime [15:8] <= u_comp[3];
mult_1 <= 159*(u_comp[3]+u_comp[2]);
mult_2 <= 52*(u_comp[4]+u_comp[1]);
mult_3 <= 21*(u_comp[5]+u_comp[0]);
u_prime [7:0] <= mult_1 - mult_2 + mult_3;
y_loc < y_loc + 18'd1
SRAM_address <= SRAM_address + 18'd1;
state <= S_READ_Y;
end
S_READ_Y: begin
y_hold <= SRAM_read_data;
r = r_hold;
g = g_hold;
b = b_hold;
v_prime [15:8] <= v_comp[3];
mult_1 <= 159*(v_comp[3]+v_comp[2]);
mult_2 <= 52*(v_comp[4]+v_comp[1]);
mult_3 <= 21*(v_comp[5]+v_comp[0]);
v_prime [7:0] <= mult_1 - mult_2 + mult_3;
uv_loc <= uv_loc + 18'd1;
SRAM_address <= U_offset + uv_loc;
state <= S_READ_U;
end
S_READ_U: begin
//still need the read u and if statement for every other clock cycle
if(u_v_toggle == 8'd0) begin // toggle == 0, then read
u_hold <= SRAM_read_data;
end
mult_1 <= 76284*(y[15:8]-16);
mult_2 <= 104595*(v_prime[15:8]-128);
mult_3 <= 132251*(u_prime[15:8]-128);
r_hold [15:8] = mult_1 + mult_2;
b_hold [15:8] = mult_1 + mult_3;
SRAM_address <= V_offset + uv_loc;
state <= S_READ_V;
end
S_READ_V: begin
if(u_v_toggle == 8'd0) begin // toggle == 0, then read
v_hold <= SRAM_read_data;
end
mult_2 <= 53281(v_prime[15:8] - 128);
mult_3 <= 25624(u_prime[15:8] - 128);
g_hold [15:8] <= mult_1 - mult_2 - mult_3;
SRAM_address <= RGB_offset + rgb_loc;
state <= S_WRITE_R;
end
S_WRITE_R: begin
mult_1 <= 76284*(y[7:0]-16);
mult_2 <= 104595*(v_prime[7:0]-128);
mult_3 <= 132251*(u_prime[7:0]-128);
r_hold [7:0] = mult_1 + mult_2;
b_hold [7:0] = mult_1 + mult_3;
u_comp[5] = u_comp[4];
u_comp[4] = u_comp[3];
u_comp[3] = u_comp[2];
u_comp[2] = u_comp[1];
u_comp[1] = u_hold[7:0];
if(lead_in == 1'b0) begin
//if its not lead in then do the write to R othewise skip it
SRAM_write_data <= r;
rgb_loc <= rgb_loc + 18'd1;
SRAM_address <= SRAM_address + rgb_loc;
end
state <= S_WRITE_G;
end
S_WRITE_G: begin
mult_2 <= 53281(v_prime[7:0] - 128);
mult_3 <= 25624(u_prime[7:0] - 128);
g_hold [7:0] <= mult_1 - mult_2 - mult_3;
if(lead_in == 1'b0) begin
SRAM_write_data <= g;
rgb_loc <= rgb_loc + 18'd1;
SRAM_address <= SRAM_address + rgb_loc;
end
v_comp[5] = v_comp[4];
v_comp[4] = v_comp[3];
v_comp[3] = v_comp[2];
v_comp[2] = v_comp[1];
v_comp[1] = v_hold[7:0];
state <= S_WRITE_B;
end
S_WRITE_B: begin
if(lead_in == 1'b0) begin
SRAM_write_data <= b;
rgb_loc <= rgb_loc + 18'd1;
SRAM_address <= SRAM_address + rgb_loc;
end
y <=y_hold;
u_prime [15:8] <= u_comp[3];
mult_1 <= 159*(u_comp[3]+u_comp[2]);
mult_2 <= 52*(u_comp[4]+u_comp[1]);
mult_3 <= 21*(u_comp[5]+u_comp[0]);
u_prime [7:0] <= mult_1 - mult_2 + mult_3;
if(lead_in==1'b1) begin
lead in <=1'b0;
end
= u_v_toggle + 8'd1;
if(u_v_toggle == 8'd2) begin //reset toggle after 2 cycles of the common case
u_v_toggle = 8'd0;
end
state <= S_READ_Y;
end
default: state <= S_IDLE;
endcase
end
end
// 7 segment displays
convert_hex_to_seven_segment unit7 (
.hex_value(SRAM_read_data[15:12]),
.converted_value(value_7_segment[7])
);
convert_hex_to_seven_segment unit6 (
.hex_value(SRAM_read_data[11:8]),
.converted_value(value_7_segment[6])
);
convert_hex_to_seven_segment unit5 (
.hex_value(SRAM_read_data[7:4]),
.converted_value(value_7_segment[5])
);
convert_hex_to_seven_segment unit4 (
.hex_value(SRAM_read_data[3:0]),
.converted_value(value_7_segment[4])
);
convert_hex_to_seven_segment unit3 (
.hex_value({2'b00, SRAM_address[17:16]}),
.converted_value(value_7_segment[3])
);
convert_hex_to_seven_segment unit2 (
.hex_value(SRAM_address[15:12]),
.converted_value(value_7_segment[2])
);
convert_hex_to_seven_segment unit1 (
.hex_value(SRAM_address[11:8]),
.converted_value(value_7_segment[1])
);
convert_hex_to_seven_segment unit0 (
.hex_value(SRAM_address[7:4]),
.converted_value(value_7_segment[0])
);
assign
SEVEN_SEGMENT_N_O[0] = value_7_segment[0],
SEVEN_SEGMENT_N_O[1] = value_7_segment[1],
SEVEN_SEGMENT_N_O[2] = value_7_segment[2],
SEVEN_SEGMENT_N_O[3] = value_7_segment[3],
SEVEN_SEGMENT_N_O[4] = value_7_segment[4],
SEVEN_SEGMENT_N_O[5] = value_7_segment[5],
SEVEN_SEGMENT_N_O[6] = value_7_segment[6],
SEVEN_SEGMENT_N_O[7] = value_7_segment[7];
assign LED_GREEN_O = {resetn, VGA_enable, ~SRAM_we_n, Frame_error, top_state};
endmodule
define_state.h:
`ifndef DEFINE_STATE
// This defines the states
typedef enum logic [1:0] {
S_IDLE,
S_ENABLE_UART_RX,
S_WAIT_UART_RX
} top_state_type;
typedef enum logic [4:0] {
S_IDLE,
S_LEAD_IN_1_U,
S_LEAD_IN_2_U,
S_LEAD_IN_3_V,
S_LEAD_IN_4_V,
S_LEAD_IN_Y,
S_WRITE_R,
S_WRITE_G,
S_WRITE_B,
S_READ_Y,
S_READ_U,
S_READ_V,
} state_type;
typedef enum logic [1:0] {
S_RXC_IDLE,
S_RXC_SYNC,
S_RXC_ASSEMBLE_DATA,
S_RXC_STOP_BIT
} RX_Controller_state_type;
typedef enum logic [2:0] {
S_US_IDLE,
S_US_STRIP_FILE_HEADER_1,
S_US_STRIP_FILE_HEADER_2,
S_US_START_FIRST_BYTE_RECEIVE,
S_US_WRITE_FIRST_BYTE,
S_US_START_SECOND_BYTE_RECEIVE,
S_US_WRITE_SECOND_BYTE
} UART_SRAM_state_type;
typedef enum logic [3:0] {
S_VS_WAIT_NEW_PIXEL_ROW,
S_VS_NEW_PIXEL_ROW_DELAY_1,
S_VS_NEW_PIXEL_ROW_DELAY_2,
S_VS_NEW_PIXEL_ROW_DELAY_3,
S_VS_NEW_PIXEL_ROW_DELAY_4,
S_VS_NEW_PIXEL_ROW_DELAY_5,
S_VS_FETCH_PIXEL_DATA_0,
S_VS_FETCH_PIXEL_DATA_1,
S_VS_FETCH_PIXEL_DATA_2,
S_VS_FETCH_PIXEL_DATA_3
} VGA_SRAM_state_type;
`define DEFINE_STATE 1
`endif
所有的状态都已经在外部文件中定义了define_state.h，应该没有任何以前的状态声明（我已经尽力检查过了。）因此，我不确定至于为什么错误仍然存在..
我已经尝试解决这个问题很长一段时间了，但无济于事。
如有任何帮助，我们将不胜感激
您有两个使用相同值的枚举类型 - S_IDLE。那是不允许的。同一范围内的枚举类型不允许共享值。您要么需要考虑一个不同的名称，要么将两个类型声明放在不同的包中。无论如何，这些类型定义最好放在一个包中，而不是像您那样使用包含文件。
typedef enum logic [1:0] {
S_IDLE, // here
S_ENABLE_UART_RX,
S_WAIT_UART_RX
} top_state_type;
typedef enum logic [4:0] {
S_IDLE, // and here
S_US_STRIP_FILE_HEADER_1,
S_US_STRIP_FILE_HEADER_2,
S_US_START_FIRST_BYTE_RECEIVE,
S_US_WRITE_FIRST_BYTE,
S_US_START_SECOND_BYTE_RECEIVE,
S_US_WRITE_SECOND_BYTE
} UART_SRAM_state_type;
我现在要做的就是克服这个错误，这样我就可以开始测试代码了，它是用于硬件图像压缩器的。
主 .v 文件：
`timescale 1ns/100ps
`ifndef DISABLE_DEFAULT_NET
`default_nettype none
`endif
`include "define_state.h"
// This is the top module
// It connects the UART, SRAM and VGA together.
// It gives access to the SRAM for UART and VGA
module experiment4a (
/////// board clocks ////////////
input logic CLOCK_50_I, // 50 MHz clock
/////// pushbuttons/switches ////////////
input logic[3:0] PUSH_BUTTON_I, // pushbuttons
input logic[17:0] SWITCH_I, // toggle switches
/////// 7 segment displays/LEDs ////////////
output logic[6:0] SEVEN_SEGMENT_N_O[7:0], // 8 seven segment displays
output logic[8:0] LED_GREEN_O, // 9 green LEDs
/////// VGA interface ////////////
output logic VGA_CLOCK_O, // VGA clock
output logic VGA_HSYNC_O, // VGA H_SYNC
output logic VGA_VSYNC_O, // VGA V_SYNC
output logic VGA_BLANK_O, // VGA BLANK
output logic VGA_SYNC_O, // VGA SYNC
output logic[7:0] VGA_RED_O, // VGA red
output logic[7:0] VGA_GREEN_O, // VGA green
output logic[7:0] VGA_BLUE_O, // VGA blue
/////// SRAM Interface ////////////
inout wire[15:0] SRAM_DATA_IO, // SRAM data bus 16 bits
output logic[19:0] SRAM_ADDRESS_O, // SRAM address bus 18 bits
output logic SRAM_UB_N_O, // SRAM high-byte data mask
output logic SRAM_LB_N_O, // SRAM low-byte data mask
output logic SRAM_WE_N_O, // SRAM write enable
output logic SRAM_CE_N_O, // SRAM chip enable
output logic SRAM_OE_N_O, // SRAM output logic enable
/////// UART ////////////
input logic UART_RX_I, // UART receive signal
output logic UART_TX_O // UART transmit signal
);
logic resetn;
top_state_type top_state;
state_type state;
// For Push button
logic [3:0] PB_pushed;
// For VGA SRAM interface
logic VGA_enable;
logic [17:0] VGA_base_address;
logic [17:0] VGA_SRAM_address;
// For SRAM
logic [17:0] SRAM_address;
logic [15:0] SRAM_write_data;
logic SRAM_we_n;
logic [15:0] SRAM_read_data;
logic SRAM_ready;
//For Milestone 1
parameter Y_offset = 0;
parameter U_offset = 38400;
parameter V_offset = 57600;
parameter RGB_offset = 146944;
logic [17:0] y_loc, uv_loc, rgb_loc;
logic [15:0] red, green, blue, r_hold, g_hold, b_hold;
logic [15:0] y, y_hold, u_prime, u_hold, v_prime, v_hold;
logic [7:0] u_comp [5:0];
logic [7:0] v_comp [5:0];
logic u_v_toggle;
logic lead_in;
logic [7:0] mult_1, mult_2, mult_3;
// For UART SRAM interface
logic UART_rx_enable;
logic UART_rx_initialize;
logic [17:0] UART_SRAM_address;
logic [15:0] UART_SRAM_write_data;
logic UART_SRAM_we_n;
logic [25:0] UART_timer;
logic [6:0] value_7_segment [7:0];
// For error detection in UART
logic [3:0] Frame_error;
// For disabling UART transmit
assign UART_TX_O = 1'b1;
assign resetn = ~SWITCH_I[17] && SRAM_ready;
// Push Button unit
PB_Controller PB_unit (
.Clock_50(CLOCK_50_I),
.Resetn(resetn),
.PB_signal(PUSH_BUTTON_I),
.PB_pushed(PB_pushed)
);
// VGA SRAM interface
logic [9:0] VGA_RED_O_long, VGA_GREEN_O_long, VGA_BLUE_O_long;
VGA_SRAM_interface VGA_unit (
.Clock(CLOCK_50_I),
.Resetn(resetn),
.VGA_enable(VGA_enable),
// For accessing SRAM
.SRAM_base_address(VGA_base_address),
.SRAM_address(VGA_SRAM_address),
.SRAM_read_data(SRAM_read_data),
// To VGA pins
.VGA_CLOCK_O(VGA_CLOCK_O),
.VGA_HSYNC_O(VGA_HSYNC_O),
.VGA_VSYNC_O(VGA_VSYNC_O),
.VGA_BLANK_O(VGA_BLANK_O),
.VGA_SYNC_O(VGA_SYNC_O),
.VGA_RED_O(VGA_RED_O_long),
.VGA_GREEN_O(VGA_GREEN_O_long),
.VGA_BLUE_O(VGA_BLUE_O_long)
);
assign VGA_RED_O = VGA_RED_O_long[9:2];
assign VGA_GREEN_O = VGA_GREEN_O_long[9:2];
assign VGA_BLUE_O = VGA_BLUE_O_long[9:2];
// UART SRAM interface
UART_SRAM_interface UART_unit(
.Clock(CLOCK_50_I),
.Resetn(resetn),
.UART_RX_I(UART_RX_I),
.Initialize(UART_rx_initialize),
.Enable(UART_rx_enable),
// For accessing SRAM
.SRAM_address(UART_SRAM_address),
.SRAM_write_data(UART_SRAM_write_data),
.SRAM_we_n(UART_SRAM_we_n),
.Frame_error(Frame_error)
);
// SRAM unit
SRAM_Controller SRAM_unit (
.Clock_50(CLOCK_50_I),
.Resetn(~SWITCH_I[17]),
.SRAM_address(SRAM_address),
.SRAM_write_data(SRAM_write_data),
.SRAM_we_n(SRAM_we_n),
.SRAM_read_data(SRAM_read_data),
.SRAM_ready(SRAM_ready),
// To the SRAM pins
.SRAM_DATA_IO(SRAM_DATA_IO),
.SRAM_ADDRESS_O(SRAM_ADDRESS_O[17:0]),
.SRAM_UB_N_O(SRAM_UB_N_O),
.SRAM_LB_N_O(SRAM_LB_N_O),
.SRAM_WE_N_O(SRAM_WE_N_O),
.SRAM_CE_N_O(SRAM_CE_N_O),
.SRAM_OE_N_O(SRAM_OE_N_O)
);
assign SRAM_ADDRESS_O[19:18] = 2'b00;
always @(posedge CLOCK_50_I or negedge resetn) begin
if (~resetn) begin
top_state <= S_IDLE;
UART_rx_initialize <= 1'b0;
UART_rx_enable <= 1'b0;
UART_timer <= 26'd0;
VGA_enable <= 1'b1;
end else begin
UART_rx_initialize <= 1'b0;
UART_rx_enable <= 1'b0;
// Timer for timeout on UART
// This counter reset itself every time a new data is received on UART
if (UART_rx_initialize | ~UART_SRAM_we_n) UART_timer <= 26'd0;
else UART_timer <= UART_timer + 26'd1;
case (top_state)
S_IDLE: begin
VGA_enable <= 1'b1;
if (~UART_RX_I | PB_pushed[0]) begin
// UART detected a signal, or PB0 is pressed
UART_rx_initialize <= 1'b1;
VGA_enable <= 1'b0;
top_state <= S_ENABLE_UART_RX;
end
end
S_ENABLE_UART_RX: begin
// Enable the UART receiver
UART_rx_enable <= 1'b1;
top_state <= S_WAIT_UART_RX;
end
S_WAIT_UART_RX: begin
if ((UART_timer == 26'd49999999) && (UART_SRAM_address != 18'h00000)) begin
// Timeout for 1 sec on UART for detecting if file transmission is finished
UART_rx_initialize <= 1'b1;
VGA_enable <= 1'b1;
top_state <= S_IDLE;
end
end
default: top_state <= S_IDLE;
endcase
end
end
assign VGA_base_address = 18'd0;
// Give access to SRAM for UART and VGA at appropriate time
assign SRAM_address = ((top_state == S_ENABLE_UART_RX) | (top_state == S_WAIT_UART_RX))
? UART_SRAM_address
: VGA_SRAM_address;
assign SRAM_write_data = UART_SRAM_write_data;
assign SRAM_we_n = ((top_state == S_ENABLE_UART_RX) | (top_state == S_WAIT_UART_RX))
? UART_SRAM_we_n
: 1'b1;
//Milestone 1
always_ff @ (posedge CLOCK_50_I or negedge resetn) begin
if (resetn == 1'b0) begin
SRAM_we_n <= 1'b1;
SRAM_write_data <= 16'd0;
SRAM_address <= 18'd0;
red = 16'd0;
green = 16'd0;
blue = 16'd0;
r_hold = 16'd0;
g_hold = 16'd0;
b_hold = 16'd0;
y = 16'd0;
y_hold = 16'd0;
u_prime = 16'd0;
u_hold = 16'd0;
u_comp [0] = 8'd0;
u_comp [1] = 8'd0;
u_comp [2] = 8'd0;
u_comp [3] = 8'd0;
u_comp [4] = 8'd0;
u_comp [5] = 8'd0;
v_prime = 16'd0;
v_hold = 16'd0;
v_comp [0] = 8'd0;
v_comp [1] = 8'd0;
v_comp [2] = 8'd0;
v_comp [3] = 8'd0;
v_comp [4] = 8'd0;
v_comp [5] = 8'd0;
u_v_toggle = 8'd0;
lead_in = 1'b1;
state <= S_IDLE;
end else begin
case (state)
S_IDLE: begin
red = 16'd0;
green = 16'd0;
blue = 16'd0;
r_hold = 16'd0;
g_hold = 16'd0;
b_hold = 16'd0;
y = 16'd0;
y_hold = 16'd0;
u_prime = 16'd0;
u_hold = 16'd0;
u_comp [0] = 8'd0;
u_comp [1] = 8'd0;
u_comp [2] = 8'd0;
u_comp [3] = 8'd0;
u_comp [4] = 8'd0;
u_comp [5] = 8'd0;
v_prime = 16'd0;
v_hold = 16'd0;
v_comp [0] = 8'd0;
v_comp [1] = 8'd0;
v_comp [2] = 8'd0;
v_comp [3] = 8'd0;
v_comp [4] = 8'd0;
v_comp [5] = 8'd0;
u_v_toggle = 8'd0;
SRAM_address <= U_offset;
uv_loc <= 18'd0;
y_loc <= 18'd0;
rgb_loc <= 18'd0;
SRAM_we_n <= 1'b0;
lead_in <=1'b1;
state <= S_LEAD_IN_1_U;
end
S_LEAD_IN_1_U: begin
u_hold <= SRAM_read_data;
u_comp [5] <=u_hold[15:8];
u_comp [4] <=u_hold[15:8];
u_comp [3] <=u_hold[15:8];
u_comp [2] <=u_hold[7:0];
SRAM_address <= SRAM_address + 18'd1;
uv_loc <= uv_loc + 18'd1;
state<= S_LEAD_IN_2_U;
end
S_LEAD_IN_2_U: begin
u_hold <= SRAM_read_data;
u_comp [1] <=u_hold[15:8];
u_comp [0] <=u_hold[7:0];
SRAM_address <= V_offset;
state<= S_LEAD_IN_3_V;
end
S_LEAD_IN_3_V: begin
v_hold <= SRAM_read_data;
v_comp [5] <=u_hold[15:8];
v_comp [4] <=u_hold[15:8];
v_comp [3] <=u_hold[15:8];
v_comp [2] <=u_hold[7:0];
SRAM_address <= SRAM_address + 18'd1;
state<= S_LEAD_IN_4_V;
end
S_LEAD_IN_4_V: begin
v_hold <= SRAM_read_data;
v_comp [1] <=u_hold[15:8];
v_comp [0] <=u_hold[7:0];
SRAM_address <= Y_offset;
state<= S_LEAD_IN_Y;
end
S_LEAD_IN_Y: begin
y = SRAM_read_data;
u_prime [15:8] <= u_comp[3];
mult_1 <= 159*(u_comp[3]+u_comp[2]);
mult_2 <= 52*(u_comp[4]+u_comp[1]);
mult_3 <= 21*(u_comp[5]+u_comp[0]);
u_prime [7:0] <= mult_1 - mult_2 + mult_3;
y_loc < y_loc + 18'd1
SRAM_address <= SRAM_address + 18'd1;
state <= S_READ_Y;
end
S_READ_Y: begin
y_hold <= SRAM_read_data;
r = r_hold;
g = g_hold;
b = b_hold;
v_prime [15:8] <= v_comp[3];
mult_1 <= 159*(v_comp[3]+v_comp[2]);
mult_2 <= 52*(v_comp[4]+v_comp[1]);
mult_3 <= 21*(v_comp[5]+v_comp[0]);
v_prime [7:0] <= mult_1 - mult_2 + mult_3;
uv_loc <= uv_loc + 18'd1;
SRAM_address <= U_offset + uv_loc;
state <= S_READ_U;
end
S_READ_U: begin
//still need the read u and if statement for every other clock cycle
if(u_v_toggle == 8'd0) begin // toggle == 0, then read
u_hold <= SRAM_read_data;
end
mult_1 <= 76284*(y[15:8]-16);
mult_2 <= 104595*(v_prime[15:8]-128);
mult_3 <= 132251*(u_prime[15:8]-128);
r_hold [15:8] = mult_1 + mult_2;
b_hold [15:8] = mult_1 + mult_3;
SRAM_address <= V_offset + uv_loc;
state <= S_READ_V;
end
S_READ_V: begin
if(u_v_toggle == 8'd0) begin // toggle == 0, then read
v_hold <= SRAM_read_data;
end
mult_2 <= 53281(v_prime[15:8] - 128);
mult_3 <= 25624(u_prime[15:8] - 128);
g_hold [15:8] <= mult_1 - mult_2 - mult_3;
SRAM_address <= RGB_offset + rgb_loc;
state <= S_WRITE_R;
end
S_WRITE_R: begin
mult_1 <= 76284*(y[7:0]-16);
mult_2 <= 104595*(v_prime[7:0]-128);
mult_3 <= 132251*(u_prime[7:0]-128);
r_hold [7:0] = mult_1 + mult_2;
b_hold [7:0] = mult_1 + mult_3;
u_comp[5] = u_comp[4];
u_comp[4] = u_comp[3];
u_comp[3] = u_comp[2];
u_comp[2] = u_comp[1];
u_comp[1] = u_hold[7:0];
if(lead_in == 1'b0) begin
//if its not lead in then do the write to R othewise skip it
SRAM_write_data <= r;
rgb_loc <= rgb_loc + 18'd1;
SRAM_address <= SRAM_address + rgb_loc;
end
state <= S_WRITE_G;
end
S_WRITE_G: begin
mult_2 <= 53281(v_prime[7:0] - 128);
mult_3 <= 25624(u_prime[7:0] - 128);
g_hold [7:0] <= mult_1 - mult_2 - mult_3;
if(lead_in == 1'b0) begin
SRAM_write_data <= g;
rgb_loc <= rgb_loc + 18'd1;
SRAM_address <= SRAM_address + rgb_loc;
end
v_comp[5] = v_comp[4];
v_comp[4] = v_comp[3];
v_comp[3] = v_comp[2];
v_comp[2] = v_comp[1];
v_comp[1] = v_hold[7:0];
state <= S_WRITE_B;
end
S_WRITE_B: begin
if(lead_in == 1'b0) begin
SRAM_write_data <= b;
rgb_loc <= rgb_loc + 18'd1;
SRAM_address <= SRAM_address + rgb_loc;
end
y <=y_hold;
u_prime [15:8] <= u_comp[3];
mult_1 <= 159*(u_comp[3]+u_comp[2]);
mult_2 <= 52*(u_comp[4]+u_comp[1]);
mult_3 <= 21*(u_comp[5]+u_comp[0]);
u_prime [7:0] <= mult_1 - mult_2 + mult_3;
if(lead_in==1'b1) begin
lead in <=1'b0;
end
= u_v_toggle + 8'd1;
if(u_v_toggle == 8'd2) begin //reset toggle after 2 cycles of the common case
u_v_toggle = 8'd0;
end
state <= S_READ_Y;
end
default: state <= S_IDLE;
endcase
end
end
// 7 segment displays
convert_hex_to_seven_segment unit7 (
.hex_value(SRAM_read_data[15:12]),
.converted_value(value_7_segment[7])
);
convert_hex_to_seven_segment unit6 (
.hex_value(SRAM_read_data[11:8]),
.converted_value(value_7_segment[6])
);
convert_hex_to_seven_segment unit5 (
.hex_value(SRAM_read_data[7:4]),
.converted_value(value_7_segment[5])
);
convert_hex_to_seven_segment unit4 (
.hex_value(SRAM_read_data[3:0]),
.converted_value(value_7_segment[4])
);
convert_hex_to_seven_segment unit3 (
.hex_value({2'b00, SRAM_address[17:16]}),
.converted_value(value_7_segment[3])
);
convert_hex_to_seven_segment unit2 (
.hex_value(SRAM_address[15:12]),
.converted_value(value_7_segment[2])
);
convert_hex_to_seven_segment unit1 (
.hex_value(SRAM_address[11:8]),
.converted_value(value_7_segment[1])
);
convert_hex_to_seven_segment unit0 (
.hex_value(SRAM_address[7:4]),
.converted_value(value_7_segment[0])
);
assign
SEVEN_SEGMENT_N_O[0] = value_7_segment[0],
SEVEN_SEGMENT_N_O[1] = value_7_segment[1],
SEVEN_SEGMENT_N_O[2] = value_7_segment[2],
SEVEN_SEGMENT_N_O[3] = value_7_segment[3],
SEVEN_SEGMENT_N_O[4] = value_7_segment[4],
SEVEN_SEGMENT_N_O[5] = value_7_segment[5],
SEVEN_SEGMENT_N_O[6] = value_7_segment[6],
SEVEN_SEGMENT_N_O[7] = value_7_segment[7];
assign LED_GREEN_O = {resetn, VGA_enable, ~SRAM_we_n, Frame_error, top_state};
endmodule
define_state.h:
`ifndef DEFINE_STATE
// This defines the states
typedef enum logic [1:0] {
S_IDLE,
S_ENABLE_UART_RX,
S_WAIT_UART_RX
} top_state_type;
typedef enum logic [4:0] {
S_IDLE,
S_LEAD_IN_1_U,
S_LEAD_IN_2_U,
S_LEAD_IN_3_V,
S_LEAD_IN_4_V,
S_LEAD_IN_Y,
S_WRITE_R,
S_WRITE_G,
S_WRITE_B,
S_READ_Y,
S_READ_U,
S_READ_V,
} state_type;
typedef enum logic [1:0] {
S_RXC_IDLE,
S_RXC_SYNC,
S_RXC_ASSEMBLE_DATA,
S_RXC_STOP_BIT
} RX_Controller_state_type;
typedef enum logic [2:0] {
S_US_IDLE,
S_US_STRIP_FILE_HEADER_1,
S_US_STRIP_FILE_HEADER_2,
S_US_START_FIRST_BYTE_RECEIVE,
S_US_WRITE_FIRST_BYTE,
S_US_START_SECOND_BYTE_RECEIVE,
S_US_WRITE_SECOND_BYTE
} UART_SRAM_state_type;
typedef enum logic [3:0] {
S_VS_WAIT_NEW_PIXEL_ROW,
S_VS_NEW_PIXEL_ROW_DELAY_1,
S_VS_NEW_PIXEL_ROW_DELAY_2,
S_VS_NEW_PIXEL_ROW_DELAY_3,
S_VS_NEW_PIXEL_ROW_DELAY_4,
S_VS_NEW_PIXEL_ROW_DELAY_5,
S_VS_FETCH_PIXEL_DATA_0,
S_VS_FETCH_PIXEL_DATA_1,
S_VS_FETCH_PIXEL_DATA_2,
S_VS_FETCH_PIXEL_DATA_3
} VGA_SRAM_state_type;
`define DEFINE_STATE 1
`endif
所有的状态都已经在外部文件中定义了define_state.h，应该没有任何以前的状态声明（我已经尽力检查过了。）因此，我不确定至于为什么错误仍然存在..
我已经尝试解决这个问题很长一段时间了，但无济于事。
如有任何帮助，我们将不胜感激
您有两个使用相同值的枚举类型 - S_IDLE。那是不允许的。同一范围内的枚举类型不允许共享值。您要么需要考虑一个不同的名称，要么将两个类型声明放在不同的包中。无论如何，这些类型定义最好放在一个包中，而不是像您那样使用包含文件。
typedef enum logic [1:0] {
S_IDLE, // here
S_ENABLE_UART_RX,
S_WAIT_UART_RX
} top_state_type;
typedef enum logic [4:0] {
S_IDLE, // and here
S_US_STRIP_FILE_HEADER_1,
S_US_STRIP_FILE_HEADER_2,
S_US_START_FIRST_BYTE_RECEIVE,
S_US_WRITE_FIRST_BYTE,
S_US_START_SECOND_BYTE_RECEIVE,
S_US_WRITE_SECOND_BYTE
} UART_SRAM_state_type;