缓存一致性和内存屏障之间有什么关系？
What is the relationship between cache coherence and memory barriers?
据我所知，使用内存屏障来避免out-of-order execution。然而，在谈论缓存一致性时，内存屏障也经常被提及。我不确定这两个概念是如何联系起来的，因为——根据我的发现——缓存一致性应该已经通过各种协议在硬件级别得到保证，例如MESI 等。使用内存屏障防止乱序执行是（手动）授予缓存一致性的另一种方式吗？
现代 CPUs 存储首先进入存储缓冲区。只有当存储离开存储缓冲区并应用于缓存行时，才会涉及缓存一致性协议。
当存储在存储缓冲区中挂起时，创建存储的 CPU 可以从存储缓冲区读回它（存储到加载转发），但其他 CPUs目前还不能观察商店的效果。
x86 等内存屏障MFENCE 等待存储缓冲区耗尽：
Performs a serializing operation on all load-from-memory and store-to-memory instructions that were issued prior the MFENCE instruction. This serializing operation guarantees that every load and store instruction that precedes the MFENCE instruction in program order becomes globally visible before any load or store instruction that follows the MFENCE instruction. The MFENCE instruction is ordered with respect to all load and store instructions, other MFENCE instructions, any LFENCE and SFENCE instructions, and any serializing instructions (such as the CPUID instruction). MFENCE does not serialize the instruction stream.
有关详细信息，请参阅 Memory Barriers: a Hardware View for Software Hackers。
据我所知，使用内存屏障来避免out-of-order execution。然而，在谈论缓存一致性时，内存屏障也经常被提及。我不确定这两个概念是如何联系起来的，因为——根据我的发现——缓存一致性应该已经通过各种协议在硬件级别得到保证，例如MESI 等。使用内存屏障防止乱序执行是（手动）授予缓存一致性的另一种方式吗？
现代 CPUs 存储首先进入存储缓冲区。只有当存储离开存储缓冲区并应用于缓存行时，才会涉及缓存一致性协议。
当存储在存储缓冲区中挂起时，创建存储的 CPU 可以从存储缓冲区读回它（存储到加载转发），但其他 CPUs目前还不能观察商店的效果。
x86 等内存屏障MFENCE 等待存储缓冲区耗尽：
Performs a serializing operation on all load-from-memory and store-to-memory instructions that were issued prior the MFENCE instruction. This serializing operation guarantees that every load and store instruction that precedes the MFENCE instruction in program order becomes globally visible before any load or store instruction that follows the MFENCE instruction. The MFENCE instruction is ordered with respect to all load and store instructions, other MFENCE instructions, any LFENCE and SFENCE instructions, and any serializing instructions (such as the CPUID instruction). MFENCE does not serialize the instruction stream.
有关详细信息，请参阅 Memory Barriers: a Hardware View for Software Hackers。