支持矢量扩展的 RISC-V 仿真器
RISC-V emulator with Vector Extension support
在哪里可以找到支持 "V" Vector Extension 的 RISC-V 仿真器？
我知道当前规范版本0.8是草案：
This is a draft of a stable proposal for the vector specification to be used for implementation and evaluation. Once the draft label is
removed, version 0.8 is intended to be stable enough to begin developing toolchains, functional simulators, and initial implementations, though will continue to evolve with minor changes and updates.
但也许某些模拟器已经提供了一些初始支持。
RISC-V spec suggests riscvOVPsim
A Complete, Fully Functional, Configurable RISC-V Simulator
...
RISC-V Specifications currently supported:
...
RISC-V Instruction Set Manual, RISC-V "V" Vector Extension (with version configurable in the model using the 'vector_version' parameter. 'master' version conforms to specification changes up to 14 December 2019 and is regularly updated to track the evolving specification.)
还有RISCV-V V extension simulator但它支持旧版本的向量扩展
RISC-V vector extension v0.7 (base) simulator implemented in C++.
官方 riscv github 频道提供了 Spike RISC-V ISA 模拟器。引用文档：
V extension, v0.9, w/ Zvlsseg/Zvamo/Zvqmac, w/o Zvediv, (requires a 64-bit host)
在哪里可以找到支持 "V" Vector Extension 的 RISC-V 仿真器？
我知道当前规范版本0.8是草案：
This is a draft of a stable proposal for the vector specification to be used for implementation and evaluation. Once the draft label is removed, version 0.8 is intended to be stable enough to begin developing toolchains, functional simulators, and initial implementations, though will continue to evolve with minor changes and updates.
但也许某些模拟器已经提供了一些初始支持。
RISC-V spec suggests riscvOVPsim
A Complete, Fully Functional, Configurable RISC-V Simulator
...
RISC-V Specifications currently supported:
...
RISC-V Instruction Set Manual, RISC-V "V" Vector Extension (with version configurable in the model using the 'vector_version' parameter. 'master' version conforms to specification changes up to 14 December 2019 and is regularly updated to track the evolving specification.)
还有RISCV-V V extension simulator但它支持旧版本的向量扩展
RISC-V vector extension v0.7 (base) simulator implemented in C++.
官方 riscv github 频道提供了 Spike RISC-V ISA 模拟器。引用文档：
V extension, v0.9, w/ Zvlsseg/Zvamo/Zvqmac, w/o Zvediv, (requires a 64-bit host)