使用命名关联的聚合排序

Aggregate Ordering with Named Association

我很难理解聚合的位顺序,特别是因为我使用了名称关联。

总线定义为 (0 to 3)(3 downto 0),但由于我使用了命名关联,为什么输出 z3..0ob3..0其他?为什么 outputs_bz_bus 相反?与从文字中分配 z_bus 相比,为什么从常量数组​​中分配 outputs_b 会对位排序产生影响?

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity Test_TB is
end entity;

architecture V1 of Test_TB is
    type TLogicLevel is (L, H, X);
    type TOutputs is array(natural range<>) of TLogicLevel;
    type TOutputsTable is array(natural range<>) of TOutputs;

    constant OUTPUTS_TABLE: TOutputsTable :=
    (
        (3 => H,  2 => H,  1 => H,  0 => L),
        (3 => X,  2 => X,  1 => X,  0 => X)  -- Added this because it can't compile an array with a single element.
    );

    signal outputs_a: TOutputs(0 to 3);
    signal outputs_b: TOutputs(3 downto 0);
    signal oa0, oa1, oa2, oa3: TLogicLevel;
    signal ob0, ob1, ob2, ob3: TLogicLevel;

    signal y_bus: TOutputs(0 to 3);
    signal z_bus: TOutputs(3 downto 0);
    signal y0, y1, y2, y3: TLogicLevel;
    signal z0, z1, z2, z3: TLogicLevel;

begin

    process
    begin
        wait for 10 ns;
        y_bus <= (3 => H, 2 => H, 1 => H, 0 => L);              -- Performs bit-for-bit copy.
        z_bus <= (3 => H, 2 => H, 1 => H, 0 => L);              -- Performs bit-for-bit copy. NOT REVERSED.
        outputs_a <= OUTPUTS_TABLE(0);                          -- Performs bit-for-bit copy.
        outputs_b <= OUTPUTS_TABLE(0);                          -- Performs bit-reverse copy. IS REVERSED.
        wait for 10 ns;
        (3 => oa3, 2 => oa2, 1 => oa1, 0 => oa0) <= outputs_a;  -- Performs bit-for-bit copy.
        (3 => ob3, 2 => ob2, 1 => ob1, 0 => ob0) <= outputs_b;  -- Performs bit-reverse copy of a reverse copy, i.e. reverse reverse.
        wait for 10 ns;
        (3 => y3, 2 => y2, 1 => y1, 0 => y0) <= y_bus;          -- Performs bit-for-bit copy.
        (3 => z3, 2 => z2, 1 => z1, 0 => z0) <= z_bus;          -- Performs bit-reverse copy of non-reverse copy. So z3..0 is the reverse of ob3..0.
        wait;
    end process;

end architecture;

您的代码表现符合我的预期。

signal y_bus: TOutputs(0 to 3);
signal z_bus: TOutputs(3 downto 0);
...
y_bus <= (3 => H, 2 => H, 1 => H, 0 => L);  
z_bus <= (3 => H, 2 => H, 1 => H, 0 => L); 

对于 y_bus,左侧位是 0,您已将其设置为 L。 对于 z_bus,左侧位是 3,您已将其设置为 H。检查。

constant OUTPUTS_TABLE: TOutputsTable :=
(
    (3 => H,  2 => H,  1 => H,  0 => L),
...
signal outputs_a: TOutputs(0 to 3);
signal outputs_b: TOutputs(3 downto 0);
....
outputs_a <= OUTPUTS_TABLE(0);
outputs_b <= OUTPUTS_TABLE(0); 

对于 OUTPUTS_TABLE(0),左侧位是 0,您已将其设置为 L。对于 outputs_a,左边的位是 0,所以你会期望它是 L。对于 outputs_b,左边的位是 3,所以你会期望它是 L。检查。

signal outputs_a: TOutputs(0 to 3);
signal outputs_b: TOutputs(3 downto 0);
...
(3 => oa3, 2 => oa2, 1 => oa1, 0 => oa0) <= outputs_a;
(3 => ob3, 2 => ob2, 1 => ob1, 0 => ob0) <= outputs_b;

对于 outputs_a 左边的位是 0,所以你会期望 oa0L,因为它是左边的那个.对于 outputs_b 左边的位是 3,所以你会期望 ob0L,因为它是左边的那个。查看。但是等一下,为什么 oa0ob0 在左边?因为这就是聚合 (3 => oa3, 2 => oa2, 1 => oa1, 0 => oa0)(3 => ob3, 2 => ob2, 1 => ob1, 0 => ob0) 中的位的编号方式,因为索引类型将是 integerinteger 类型计数。

signal y_bus: TOutputs(0 to 3);
signal z_bus: TOutputs(3 downto 0);
....
y_bus <= (3 => H, 2 => H, 1 => H, 0 => L); 
z_bus <= (3 => H, 2 => H, 1 => H, 0 => L); 
....
(3 => y3, 2 => y2, 1 => y1, 0 => y0) <= y_bus;
(3 => z3, 2 => z2, 1 => z1, 0 => z0) <= z_bus;

所以,正如我们已经知道的,对于 y_bus,左侧位是 0,您已将其设置为 L,对于 z_bus,左侧位是 3,您已将其设置为 H。因此,您会期望 y0(左侧位)为 L,而 z0(左侧位)为 H。检查。

我头疼