运行 OpenOCD 因 jtagRocketConfig 而失败
Running OpenOCD fails with jtagRocketConfig
这是我尝试连接软件 RTL 模拟和 OpenOCD 时得到的结果:
xPack OpenOCD, x86_64 Open On-Chip Debugger 0.10.0+dev-00068-ge1e63ef30 (2020-03-16-05:57)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
Info : only one transport option; autoselect 'jtag'
Info : Initializing remote_bitbang driver
Info : Connecting to localhost:38000
Info : remote_bitbang driver initialized
Info : This adapter doesn't support configurable speed
Error: fflush: Broken pipe
Error: read: count=-1, error=Broken pipe
Error: Trying to use configured scan chain anyway...
Error: fflush: Broken pipe
Error: fflush: Broken pipe
Warn : Bypassing JTAG setup events due to errors
Error: fflush: Broken pipe
Error: fflush: Broken pipe
Error: failed jtag scan: -4
Error: Unsupported DTM version: 12
Info : Listening on port 3333 for gdb connections
Error: Target not examined yet
Error: Unsupported DTM version: 12
Error: fflush: Broken pipe
Error: failed: -4
我应用了 8.2.2.1. Creating a DTM+JTAG Config 中的说明。
OpenOCD配置文件内容如下:
interface remote_bitbang
remote_bitbang_host localhost
remote_bitbang_port 38000
set _CHIPNAME riscv
jtag newtap $_CHIPNAME cpu -irlen 5
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME riscv -chain-position $_TARGETNAME
gdb_report_data_abort enable
init
halt
这是我用来运行模拟的命令:
./simulator-chipyard-jtagRocketConfig +jtag_rbb_enable=1 --rbb-port=38000 <TESTNAME>
我设法 运行 OpenOCD。
这是 OpenOCD 配置文件的当前内容:
adapter_khz 10000
interface remote_bitbang
remote_bitbang_host $::env(REMOTE_BITBANG_HOST)
remote_bitbang_port $::env(REMOTE_BITBANG_PORT)
set _CHIPNAME riscv
jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME riscv -chain-position $_TARGETNAME
$_TARGETNAME configure -work-area-phys $::env(WORK_AREA) -work-area-size 8096 -work-area-backup 1
gdb_report_data_abort enable
gdb_report_register_access_error enable
# Expose an unimplemented CSR so we can test non-existent register access
# behavior.
riscv expose_csrs 2288
riscv expose_custom 1,12345-12348
init
set challenge [riscv authdata_read]
riscv authdata_write [expr $challenge + 1]
halt
这就是我 运行 OpenOCD 的方式:
REMOTE_BITBANG_HOST=localhost REMOTE_BITBANG_PORT=38000 WORK_AREA=0x1212340000 openocd --command 'gdb_port 0' --command 'tcl_port disabled' --command 'telnet_port disabled' -f openocd.cfg
我还安装了 Verilator (v4.028)。
这是我尝试连接软件 RTL 模拟和 OpenOCD 时得到的结果:
xPack OpenOCD, x86_64 Open On-Chip Debugger 0.10.0+dev-00068-ge1e63ef30 (2020-03-16-05:57)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
Info : only one transport option; autoselect 'jtag'
Info : Initializing remote_bitbang driver
Info : Connecting to localhost:38000
Info : remote_bitbang driver initialized
Info : This adapter doesn't support configurable speed
Error: fflush: Broken pipe
Error: read: count=-1, error=Broken pipe
Error: Trying to use configured scan chain anyway...
Error: fflush: Broken pipe
Error: fflush: Broken pipe
Warn : Bypassing JTAG setup events due to errors
Error: fflush: Broken pipe
Error: fflush: Broken pipe
Error: failed jtag scan: -4
Error: Unsupported DTM version: 12
Info : Listening on port 3333 for gdb connections
Error: Target not examined yet
Error: Unsupported DTM version: 12
Error: fflush: Broken pipe
Error: failed: -4
我应用了 8.2.2.1. Creating a DTM+JTAG Config 中的说明。
OpenOCD配置文件内容如下:
interface remote_bitbang
remote_bitbang_host localhost
remote_bitbang_port 38000
set _CHIPNAME riscv
jtag newtap $_CHIPNAME cpu -irlen 5
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME riscv -chain-position $_TARGETNAME
gdb_report_data_abort enable
init
halt
这是我用来运行模拟的命令:
./simulator-chipyard-jtagRocketConfig +jtag_rbb_enable=1 --rbb-port=38000 <TESTNAME>
我设法 运行 OpenOCD。
这是 OpenOCD 配置文件的当前内容:
adapter_khz 10000
interface remote_bitbang
remote_bitbang_host $::env(REMOTE_BITBANG_HOST)
remote_bitbang_port $::env(REMOTE_BITBANG_PORT)
set _CHIPNAME riscv
jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME riscv -chain-position $_TARGETNAME
$_TARGETNAME configure -work-area-phys $::env(WORK_AREA) -work-area-size 8096 -work-area-backup 1
gdb_report_data_abort enable
gdb_report_register_access_error enable
# Expose an unimplemented CSR so we can test non-existent register access
# behavior.
riscv expose_csrs 2288
riscv expose_custom 1,12345-12348
init
set challenge [riscv authdata_read]
riscv authdata_write [expr $challenge + 1]
halt
这就是我 运行 OpenOCD 的方式:
REMOTE_BITBANG_HOST=localhost REMOTE_BITBANG_PORT=38000 WORK_AREA=0x1212340000 openocd --command 'gdb_port 0' --command 'tcl_port disabled' --command 'telnet_port disabled' -f openocd.cfg
我还安装了 Verilator (v4.028)。