VHDL 输出端口上不存在驱动程序

Question

我正在用 VHDL 做我的第一个项目，我尝试使用多路复用器实现 8 位桶形移位器。

这是一个块的代码（链中有 8 个多路复用器）：

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.sample_package.all;
-------------------------------------
ENTITY Shifter IS
  GENERIC (n : INTEGER );
  PORT (    x,y: IN STD_LOGIC_VECTOR (n-1 DOWNTO 0);
            redB: IN Integer;
            out_m: OUT STD_LOGIC_VECTOR(n-1 downto 0));
END Shifter;
--------------------------------------------------------------
ARCHITECTURE dfl OF Shifter IS
SIGNAL sm : STD_LOGIC;
SIGNAL what_b : STD_LOGIC;
BEGIN   
  --redB in the number of the red block in the diagram
  --The first mux port map is the same for all three blocks
  sm <= y(redB); 
    first : MUX port map(
            a => x(0),
            b => '0',
            s0 => sm,
            y => out_m(0)
    );

    b0: if redB=0 generate                             --First block - only the first mux has b=0
    rest : for i in 1 to n-1 generate
          chain : MUX port map(
            a => x(i),
            b => x(i-1),
            s0 => sm,
            y => out_m(i)
          );
     end generate;
    end generate;

    b1: if redB=1 generate 
    rest : for i in 1 to n-1 generate
        what_b <= '0' when i=1 else                    --Second block - 2 first mux has b=0
                      x(i-2);                                              
          chain : MUX port map(
            a => x(i),
            b => what_b,
            s0 => sm,
            y => out_m(i)
          );
     end generate;
    end generate;

    b2: if redB=2 generate 
    rest : for i in 1 to n-1 generate
       what_b <= '0' when i=1 or i=2 or i=3 else       --Third block - 4 first mux has b=0  
                 x(i-4);
          chain : MUX port map(
            a => x(i),
            b => what_b,
            s0 => sm,
            y => out_m(i)
          );
     end generate;
    end generate;

END dfl;

这是更换 3 个变速杆的代码：


LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.sample_package.all;

-------------------------------------
ENTITY Barrel IS
  GENERIC (n : INTEGER);
  PORT (    x,y: IN STD_LOGIC_VECTOR (n-1 DOWNTO 0);
            out_shifter0,out_shifter1,out_shifter2: OUT STD_LOGIC_VECTOR(n-1 downto 0));
END Barrel;
--------------------------------------------------------------
ARCHITECTURE dfl OF Barrel IS
SIGNAL temp_out0 : std_logic_vector(n-1 DOWNTO 0);
SIGNAL temp_out1 : std_logic_vector(n-1 DOWNTO 0);
SIGNAL temp_out2 : std_logic_vector(n-1 DOWNTO 0);
BEGIN

  y0: Shifter GENERIC MAP(n) port map (x=>x,y=>y,redB=>0,out_m=>temp_out0);
  out_shifter0 <= temp_out0;
  y1: Shifter GENERIC MAP(n) port map (x=>temp_out0,y=>y,redB=>1,out_m=>temp_out1);
  out_shifter1 <= temp_out1;
  y2: Shifter GENERIC MAP(n) port map (x=>temp_out1,y=>y,redB=>2,out_m=>temp_out2);
  out_shifter2 <= temp_out2;

END dfl;

所有文件都在编译，但是当我尝试运行模拟时，我收到此警告：

# ** Warning: (vsim-8684) No drivers exist on out port /tb/L0/y1/out_m(7 downto 1), and its initial value is not used.
# 
# Therefore, simulation behavior may occur that is not in compliance with
# 
# the VHDL standard as the initial values come from the base signal /tb/L0/temp_out1(7 downto 1).

我正在使用 ModelSim。任何人都知道可能是什么问题吗？

谢谢！

Answer 1

您已经完成了一个带有信号的生成，并将其值与某物进行了比较。整数初始化为 -2^31，因此 none 的生成块存在，因为您在外部分配的值直到模拟开始后才分配，但生成是在详细说明期间创建的（在模拟开始之前）使用 redB 的初始值。因此 out_m 没有驱动程序。不要在生成条件中使用信号，而是使用泛型，因为它们的值是固定的并在详细说明期间分配。

VHDL 输出端口上不存在驱动程序

VHDL No drivers exist on out port

simulation

warnings

vhdl

modelsim