输出中的 Verilog 仿真 x

Question

我有一些verilog问题，无法解决。尝试了不同的更改，但仍然没有解决方案。

代码：

module Perpetual_Calender();

 reg [3:0] year[277:0]; //14 different calendars can exist for 2033-1755 = 288 years 
 reg [2:0] month[3:0][3:0]; //different calenders for combination of year and month
 reg [2:0] day [2:0][4:0]; //different days for combination of calender and day of month.

 reg Error;

 reg[0:3] c; reg[0:2] f, g; 

 integer i,j;

 // fot Year 0 = A, 1 = B... 13 = N

  task Show_corresponding_day;
    input integer m;
    input integer d;
    input integer y;
    begin

      Error = 0;

      $display("# (m/d/y) %d/%d/%d = ",m,d,y);

      if(y<1755 || y>2033 || m<1 || m>12 || d<1 || d>31)
        Error = 1;

     if(!Error) begin  
     c = year[y-1755];
     f = month[c][m];

     $display("c = %d, f = %d", c, f);

     if(d > 29 + month[c][m+1] - (f+1)%7)
       Error = 1; 

     if(!Error)
     g = day[f][d];

     $display("g = %d", g);
     end   

     case({Error, g})  

     4'd1: $display("Monday\n");
     4'd2: $display("Tuesday\n");
     4'd3: $display("Wednesday\n");
     4'd4: $display("Thrusday\n");
     4'd5: $display("Friday\n");
     4'd6: $display("Saturday\n");
     4'd7: $display("Sunday\n");
     default: $display("ERROR\n"); 

    endcase

  end  
  endtask

 initial begin

 year[0] = 4'd2;

 for(i = 1756; i<=2033; i=i+1) begin

  if(year[i-1756] > 6)
   year[i-1755] = (year[i-1756]+2)%7;
 else
   year[i-1755] = (year[i-1756]+1)%7;

   j = i%4;
   if(i != 1800 && i  != 1900 && j == 0)
     year[i-1755] = year[i-1756]+7;  
 end

 for(i = 0; i<7; i=i+1) begin

   month[i][1] = i; month[i][2] = (i+31)%7;

   month[i][3] = (month[i][2]+28)%7; month[i][4] = (month[i][3]+31)%7; $display("m = %b, n = %b\n", month[i][4], (month[i][3]+31)%7);

   month[i][5] = (month[i][4]+30)%7; month[i][6] = (month[i][5]+31)%7;

   month[i][7] = (month[i][6]+30)%7; month[i][8] = (month[i][7]+31)%7;

   month[i][9] = (month[i][8]+31)%7; month[i][10] = (month[i][9]+30)%7;

   month[i][11] = (month[i][10]+31)%7; month[i][12] = (month[i][11]+30)%7;

   month[i][13] = (month[i][12]+31)%7; // used only in checking for errors  

 end



 for(i = 7; i<14; i=i+1) begin

  month[i][1] = i%7; month[i][2] = (i+31)%7;

   month[i][3] = (month[i][2]+29)%7; month[i][4] = (month[i][3]+31)%7;

   month[i][5] = (month[i][4]+30)%7; month[i][6] = (month[i][5]+31)%7;

   month[i][7] = (month[i][6]+30)%7; month[i][8] = (month[i][7]+31)%7;

   month[i][9] = (month[i][8]+31)%7; month[i][10] = (month[i][9]+30)%7;

   month[i][11] = (month[i][10]+31)%7; month[i][12] = (month[i][11]+30)%7;

   month[i][13] = (month[i][12]+31)%7; // used only in checking for errors    

 end

 for(i = 0; i <7; i=i+1) begin

   for(j=1; j<32; j=j+1) begin

   day[i][j] = (i+j-1)%7+1;


end

 end

 Show_corresponding_day(7,31,2001);
 Show_corresponding_day(1,25,1987);
 Show_corresponding_day(4,31,2008);
 Show_corresponding_day(2,29,2005);
 Show_corresponding_day(6,30,2013);
 Show_corresponding_day(13,27,2013);
 Show_corresponding_day(11,30,1001);
 Show_corresponding_day(3,27,2012);

 end

endmodule

部分输出：

# m = xxx, n = 00000000000000000000000000000110
# 
# m = xxx, n = 00000000000000000000000000000000
# 
# m = xxx, n = 00000000000000000000000000000001
# 
# m = xxx, n = 00000000000000000000000000000010
# 
# m = xxx, n = xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
# 
# m = xxx, n = xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
# 
# m = xxx, n = xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx

输出中为什么或如何输出 x？模块总和显示正确，但寄存器的输出仅为 x。

Answer 1

显示问题的小例子：

module tb;
  reg [2:0] month[3:0][3:0];

  initial begin
    month[0][2] = 3'b011;
    month[0][3] = (month[0][2]+28)%7;
    month[0][4] = (month[0][3]+31)%7;

    $display("2: %b", month[0][2]);
    $display("3: %b", month[0][3]);
    $display("4: %b", month[0][4]);
  end

endmodule

当定义为 reg [2:0] month[3:0][3:0];

时，你遇到的问题是 month[0][4]

您最多可以将 month[0][0] 地址设为 month[3][3]，超出此范围的任何地址都将超出范围。

另请注意，当我运行你的完整代码时，我收到许多数组索引越界警告。

你至少要定义：reg [2:0] month[6:0][13:1];交换数组位的顺序也更常见，即：

reg [2:0] month[0:6][1:13];

输出中的 Verilog 仿真 x

Verilog simulation x's in output

verilog

simulation

hdl

modelsim