Verilog for循环无法使用oasys进行合成

Question

我不知道为什么这段代码使用oasys工具合成失败

 for (i = 0; i < N; i = i + 1) begin
          if( i >= counter & i < new_pos)
            out[i] <= bit;
        end

其中 counter,out 是 reg，new_pos 是 wire 对于下面提供的完整代码模块

module decompressor #(parameter N = 32)(clk ,  reset , start , bit , value 
 , store , out);
  input clk,reset,start,bit; // start decompress , bit is the value to be 
  added
  input [$clog2(N):0] value; // value is counter for the decoded bit
  output reg store;  // Store to acknwoledge memory manager
 output reg[N-1:0]out;  // out is decoded data
  reg [$clog2(N) - 1:0] counter,counter2; // counter for number of 
 decompressed bits
 wire [$clog2 (N) + 1:0] new_pos , remain , new_value , temp ,full; // 
new_pos is new counter after decompress & remain number of uncompressed 
 bits
  reg next; // finished decompressing
 wire work ;  // Haven't finished decompressing
  integer i;  // used in for loop

  assign full = N;

  adder #($clog2 (N) + 1) add1(new_value , {2'b00 ,counter2} , new_pos);
 sub #($clog2 (N) + 1) sub1(full , {2'b00 , counter2} , remain);
 sub #($clog2 (N) + 1) sub2({1'b0,value} , remain , temp);

 assign new_value = (start == 1)? {1'b0,value} : temp;
 assign work = (~next) | start;

 always @( posedge clk , reset)begin
   if(reset == 1'b1)begin
    counter <= 0;
    counter2 <= 0;
    next <= 0;
  end else if(work == 1'b1) begin
    if( new_pos <= N )begin
      for (i = 0; i < N; i = i + 1) begin
          if( i >= counter & i < new_pos)
            out[i] <= bit;
        end
      counter <= new_pos[$clog2(N) - 1:0]; 
      next <= 1'b1;
      if( new_pos ==  N)begin 
        store <= 1'b1;
      end else begin
        store <= 1'b0;
      end
    end else begin
      for (i = 0; i < N; i = i + 1) begin
          if( i >= counter )
            out[i] <= bit;
        end
      counter <= 0;
      next <= 0;
      store <= 1'b1;
    end   
  end else 
    store <= 1'b0;
end

always @(negedge clk)begin
if( reset == 1'b0) 
  counter2 <= counter;
end

结束模块

Answer 1

always @( posedge clk , reset) 不是用于合成的有效事件列表。试试 always @(posedge clk, posedge reset).

Verilog for循环无法使用oasys进行合成

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