ShiftRegister Verilog HDL 输出给出 xxxxxxx

Question

我正尝试在 Verilog HDL 中创建一个 64 位移位寄存器。当我在测试平台中尝试代码时，我只得到 xxxxxx 作为输出，直到所有位都被移位。我不知道是什么问题。这是我的测试平台代码和结果：

module ShiftRegister (shift_out, clk, shift_in); //module ports
  parameter n = 64; //Parameter n declared to store 64
  input [n-1:0] shift_in; //64-bit input shift_in
  input clk; //Input clock
  output [n-1:0] shift_out; //64-bit output shift_out
  reg [n-1:0] ff; //64-bit flipflop
  assign shift_out = ff [n-1:0]; //give the output of the 64th bit
  //The operation of verilog: 
   always @ (posedge clk) //Always at the rising edge of the clock
   begin
     ff <= ff << 1;  //Shift bits to the left by 1
     ff[0] <= shift_in; //Take the input bits and give it to the first flipflop
     end
endmodule //ShiftRegister module

///Testbench\\ 
module ShiftRegister_tb; //Module shiftRegister_tb
   parameter n = 64; //Parameter n declared to store 64
   reg [n-1:0] shift_in; //64-bit register input shift_in
   reg clk, rst; //register clock
   wire [n-1:0] shift_out; //64-bit wire output shift_out
   ShiftRegister DUT(shift_out, clk, shift_in); //Calling the module
  initial
    begin
    clk = 0; //clock = 0 initally
    shift_in = 64'd34645767785344; //Random decimal number to test the code 
    #100;
   end
 always #50 clk =~clk; //invert the clock input after 50ps
endmodule //ShiftRegister testbench

Answer 1

您将 ff 声明为 reg，reg 的默认值为 x。在时钟的第一个姿势之前，ff 的所有 64 位都是 x（未知）。在时钟的第一个 posedge 之后，ff[0] 变为 0，因为 shift_in[0] 为 0。依此类推，直到达到 64 个时钟，然后所有 ff 位都为 0。 shift_out紧随 ff.

通常，您的设计也会有一个复位信号。如果你有一个，你可以在开始时断言重置，并在重置期间将 ff 分配给 0。这是重置后的样子：

module ShiftRegister (shift_out, clk, shift_in, rst); //module ports
    parameter n = 64; //Parameter n declared to store 64
    input rst;
    input [n-1:0] shift_in; //64-bit input shift_in
    input clk; //Input clock
    output [n-1:0] shift_out; //64-bit output shift_out
    reg [n-1:0] ff; //64-bit flipflop
    assign shift_out = ff [n-1:0]; //give the output of the 64th bit

    always @ (posedge clk or posedge rst) //Always at the rising edge of the clock
    begin
        if (rst) begin
            ff <= 0;
        end else begin
            ff <= ff << 1;  //Shift bits to the left by 1
            ff[0] <= shift_in; //Take the input bits and give it to the first flipflop
        end
    end
endmodule

module ShiftRegister_tb; //Module shiftRegister_tb
    parameter n = 64; //Parameter n declared to store 64
    reg [n-1:0] shift_in; //64-bit register input shift_in
    reg clk, rst; //register clock
    wire [n-1:0] shift_out; //64-bit wire output shift_out
    ShiftRegister DUT(shift_out, clk, shift_in,rst); //Calling the module
    initial
    begin
        clk = 0; //clock = 0 initally
        rst = 1;
        shift_in = 64'd34645767785344; //Random decimal number to test the code 
        #100;
        rst = 0;
        #50_000 $finish;
    end
    always #50 clk =~clk; //invert the clock input after 50ps
endmodule

ShiftRegister Verilog HDL 输出给出 xxxxxxx

ShiftRegister Verilog HDL Output giving xxxxxxx

verilog

hdl

shift-register