STM32H7 MPU可共享内存属性和强序内存类型
STM32H7 MPU shareable memory attribute and strongly ordered memory type
我对STM32H7 MPU的一些属性感到困惑
我已经阅读了几个文档：STM32H7 参考和编程手册、STMicro 关于 MPM 的应用说明等...
我了解到可共享完全等同于不可缓存（至少在单核 STM32H7 上）。正确吗？
我需要为 QSPI 闪存定义一个 MPU 区域。来自 MicroChip 的文档（参考资料 TB3179）指出 QSPI 存储器应配置为严格有序。我真的不明白为什么？
Question: I've understood that shareable is exactly equivalent to non-cacheable (at least on a single core STM32H7). Is it correct?
这是 MPU 配置的 ST 指南：
If some area is Cacheable and Shareable, only instruction cache is used in STM32F7/H7
As STM32 [F7 and H7] microcontrollers don't contain any hardware
feature for keeping data coherent, setting a region as Shareable
means that data cache is not used in the region. If the region is not
shareable, data cache can be used, but data coherency between bus
masters need to be ensured by software.
当INSTRUCTION_ACCESS_DISABLED（从不执行，禁用代码执行）时，STM32H7 上的可共享似乎隐含地与非缓存访问同义。
此外，
The sharability attribute tells the processor it must do whatever
is necessary to allow that data to be shared. What that really
means depends on the features of a particular processor.
On a processor with multi-CPU hardware cache coherency; the
shareability attribute is a signal to engage the cache coherency logic.
For example A57 can maintain cache-coherency of shareable data within
the cluster and between clusters if connected via a coherent
interconnect.
On a processor without hardware cache coherency, such as Cortex-A8, the only way to share the data is to push it out of the
cache as you guessed. On A8 shareable, cacheable memory ends up
being treated as un-cached.
有人，如果我错了，请纠正我 - 很难就这个主题给出明确而简洁的陈述。
Question: I need to define an MPU region for a QSPI Flash memory.
QSPI memory should be configured as Strongly Ordered. I don't really understand why?
上面的 MPU 指南至少声明了两点：防止推测访问并防止写入碎片（例如被读取操作中断）。
Speculative memory read may cause high latency or even system error
when performed on external memories like SDRAM, or Quad-SPI.
External memories even don't need to be connected to the microcontroller,
but its memory range is accessible by speculative read because by
default, its memory region is set as Normal.
Speculative access is never made to Strongly Ordered and Device memory
areas.
Strongly Ordered memory type is used in memories which need to have each write be a single transaction
For Strongly Ordered memory region CPU waits for the end of memory access instruction.
最后，我怀疑对齐可能是内存方面的一项要求，它由强制对齐 read/write 访问的内存类型充分表示。
However, Device and Strongly-ordered memory are always Non-cacheable.
Also, any unaligned access to Device or Strongly-ordered memory
generates alignment UsageFault and therefore does not cause any AXI
transfer. This means that the access examples are given in this chapter
never show unaligned accesses to Device or Strongly-ordered memory.
UsageFault ：如果没有显式配置，UsageFault 默认调用 HardFault 处理程序。需要先在 SCB 系统处理程序控制和状态寄存器 中启用差异化错误处理：
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk // will also be set by HAL_MPU_Enable()
| SCB_SHCSR_BUSFAULTENA_Msk
| SCB_SHCSR_USGFAULTENA_Msk;
UsageFault 处理程序可以评估 https://www.keil.com/appnotes/files/apnt209.pdf 中描述的 UsageFault 状态寄存器 (UFSR)。
printf("UFSR : 0x%4x\n", (SCB->CFSR >> 16) & 0xFFFF);
我对STM32H7 MPU的一些属性感到困惑
我已经阅读了几个文档：STM32H7 参考和编程手册、STMicro 关于 MPM 的应用说明等...
我了解到可共享完全等同于不可缓存（至少在单核 STM32H7 上）。正确吗？
我需要为 QSPI 闪存定义一个 MPU 区域。来自 MicroChip 的文档（参考资料 TB3179）指出 QSPI 存储器应配置为严格有序。我真的不明白为什么？
Question: I've understood that shareable is exactly equivalent to non-cacheable (at least on a single core STM32H7). Is it correct?
这是 MPU 配置的 ST 指南：
If some area is Cacheable and Shareable, only instruction cache is used in STM32F7/H7
As STM32 [F7 and H7] microcontrollers don't contain any hardware feature for keeping data coherent, setting a region as Shareable means that data cache is not used in the region. If the region is not shareable, data cache can be used, but data coherency between bus masters need to be ensured by software.
当INSTRUCTION_ACCESS_DISABLED（从不执行，禁用代码执行）时，STM32H7 上的可共享似乎隐含地与非缓存访问同义。
此外，
The sharability attribute tells the processor it must do whatever is necessary to allow that data to be shared. What that really means depends on the features of a particular processor.
On a processor with multi-CPU hardware cache coherency; the shareability attribute is a signal to engage the cache coherency logic. For example A57 can maintain cache-coherency of shareable data within the cluster and between clusters if connected via a coherent interconnect.
On a processor without hardware cache coherency, such as Cortex-A8, the only way to share the data is to push it out of the cache as you guessed. On A8 shareable, cacheable memory ends up being treated as un-cached.
有人，如果我错了，请纠正我 - 很难就这个主题给出明确而简洁的陈述。
Question: I need to define an MPU region for a QSPI Flash memory. QSPI memory should be configured as Strongly Ordered. I don't really understand why?
上面的 MPU 指南至少声明了两点：防止推测访问并防止写入碎片（例如被读取操作中断）。
Speculative memory read may cause high latency or even system error when performed on external memories like SDRAM, or Quad-SPI.
External memories even don't need to be connected to the microcontroller, but its memory range is accessible by speculative read because by default, its memory region is set as Normal.
Speculative access is never made to Strongly Ordered and Device memory areas.
Strongly Ordered memory type is used in memories which need to have each write be a single transaction
For Strongly Ordered memory region CPU waits for the end of memory access instruction.
最后，我怀疑对齐可能是内存方面的一项要求，它由强制对齐 read/write 访问的内存类型充分表示。
However, Device and Strongly-ordered memory are always Non-cacheable. Also, any unaligned access to Device or Strongly-ordered memory generates alignment UsageFault and therefore does not cause any AXI transfer. This means that the access examples are given in this chapter never show unaligned accesses to Device or Strongly-ordered memory.
UsageFault ：如果没有显式配置，UsageFault 默认调用 HardFault 处理程序。需要先在 SCB 系统处理程序控制和状态寄存器 中启用差异化错误处理：
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk // will also be set by HAL_MPU_Enable()
| SCB_SHCSR_BUSFAULTENA_Msk
| SCB_SHCSR_USGFAULTENA_Msk;
UsageFault 处理程序可以评估 https://www.keil.com/appnotes/files/apnt209.pdf 中描述的 UsageFault 状态寄存器 (UFSR)。
printf("UFSR : 0x%4x\n", (SCB->CFSR >> 16) & 0xFFFF);