vhdl中的多路复用器结构设计

Question

我对 VHDL 完全陌生，我想实现以下 MUX 用于逻辑 implication S0 => S1 不使用其他门。

我想使用结构设计，但我的主要问题之一是我不知道如何正确映射端口，以便我实现给定的含义。

到目前为止，我的代码正在编译并且 iSim 已启动，但我收到两个警告：

mux41_impl 仍然是一个黑盒，因为它没有绑定实体。
mux_out_test 的值为 U

此外，我了解我的组件必须与实体完全匹配但如果我将其重命名为实体名称，我将收到非法递归消息。

代码

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity MUX41_IMPL_top is
port (
    D0, D1, D2, D3, S0, S1: in STD_LOGIC;
    mux_out : out STD_LOGIC
);
end MUX41_IMPL_top;

architecture structure of MUX41_IMPL_top is

component MUX41_IMPL
    port (
        D0, D1, D2, D3, S0, S1: in STD_LOGIC;
        mux_out : out STD_LOGIC
    );
end component;

begin

u1: MUX41_IMPL port map (D0, D1, D2, D3, S0, S1, mux_out);
end structure;

测试台代码

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity MUX41_IMPL_SIMBOX is
end MUX41_IMPL_SIMBOX;

architecture TEST_MUX41_IMPL of MUX41_IMPL_SIMBOX is

component MUX41_IMPL is
    port (
        D0, D1, D2, D3, S0, S1: in STD_LOGIC;
        mux_out : out STD_LOGIC
    );
end component;

signal D0_test : STD_LOGIC := '1';
signal D1_test : STD_LOGIC := '0';
signal D2_test : STD_LOGIC := '1';
signal D3_test : STD_LOGIC := '1';
signal S0_test, S1_test : STD_LOGIC := '0';
signal mux_out_test : STD_LOGIC;

for my_MUX41_IMPL : MUX41_IMPL use entity work.MUX41_IMPL_top(structure);

begin
    my_MUX41_IMPL : MUX41_IMPL
    port map (
    D0 => D0_test,
    D1 => D1_test,
    D2 => D2_test,
    D3 => D3_test,
    S0 => S0_test,
    S1 => S1_test,
    mux_out => mux_out_test
    );

    S0_test <= not S0_test after 2 ns;
    S1_test <= not S1_test after 4 ns;

end TEST_MUX41_IMPL;

Answer 1

entity MUX41_IMPL_top is
port (
    D0, D1, D2, D3: in STD_LOGIC;
    Sel : in std_logic_vector(1 downto 0);    
    mux_out : out STD_LOGIC

);
end MUX41_IMPL_top;

architecture structure of MUX41_IMPL_top is
begin

with Sel select
    mux_out <=  D0 when "00",
                D1 when "01",
                D2 when "10",            
                D3 when "11",            
                '0' when others;    

architecture structure;

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