如何在VHDL中添加两个16位STD_LOGIC_VECTOR和一个进位到17位？

Question

我有两个输入16位LOGIC_VECTOR A,B和一个Cin:

A,B : in STD_LOGIC_VECTOR(15 DOWNTO 0);
Cin : in STD_LOGIC;
F : out STD_LOGIC_VECTOR(15 downto 0);
Cout : out STD_LOGIC

和17位LOGIC_VECTOR结果信号：

signal result : STD_LOGIC_VECTOR(16 DOWNTO 0);

以及添加 A 和 B 以及 Cin 的以下代码：

result <= ('0' & A) + ('0' & B) + Cin;
F <= result(15 DOWNTO 0);
Cout <= result(16);

但它只是添加了 A、B，而 Cin 被忽略了。我怎样才能做到这一点？

测试台：

A <= "1010100101110011";
B <= "0001111101010101";
Cin <= '1';

但是 F 是：

1100100011001000

Answer 1

验证您的连接，您的代码可以正常工作。我尝试了以下方法：

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity adder is
    port (
        A, B : in  std_logic_vector(15 downto 0);
        Cin  : in  std_logic;
        F    : out std_logic_vector(15 downto 0);
        Cout : out std_logic
    );
end entity adder;

architecture rtl of adder is
    signal result : std_logic_vector(16 downto 0);
begin
    result <= ('0' & A) + ('0' & B) + Cin;
    F      <= result(15 downto 0);
    Cout   <= result(16);
end architecture rtl;

library ieee;
use ieee.std_logic_1164.all;

entity adder_tb is
end entity adder_tb;

architecture behavioral of adder_tb is
    signal A, B, F : std_logic_vector(15 downto 0);
    signal Cin, Cout : std_logic;
begin

    DUT: entity work.adder
    port map (
        A    => A,
        B    => B,
        Cin  => Cin,
        F    => F,
        Cout => Cout
    );

    A   <= "1010100101110011";
    B   <= "0001111101010101";
    Cin <= '1';

end architecture behavioral;

并得到：

其中 F = 1100100011001001，符合预期。

如何在VHDL中添加两个16位STD_LOGIC_VECTOR和一个进位到17位？

how to add two 16-bit STD_LOGIC_VECTOR and a carry into 17-bit in VHDL?

vhdl