Verilog 临时变量

Question

我试图在 Verilog 中制作 CMP 指令。为了保留减法的结果，我声明了一条线。这就是代码的样子（它在 always 语句中执行）。

wire [data_width:0] tmp_wire = reg_accumulator - reg_x;

f_zero <= tmp_wire & 'hFF == 0;
f_carry <= tmp_wire & 'h100;

现在 Icarus Verilog 抱怨语法错误并且 reg_accumulator - reg_x 不是 l-value:

cpu.v:149: syntax error
cpu.v:149: Syntax in assignment statement l-value.

它为什么抱怨？在函数/任务中声明临时变量的正确方法是什么？

module comparator(
    input clk,
    input [7:0] op_a,
    input [7:0] op_b
);

reg f_zero;
reg f_carry;

function compare;
    input [data_width-1:0] a;
    input [data_width-1:0] b;
begin
    wire [7:0] tmp_wire = reg_accumulator - reg_x;

    f_zero <= tmp_wire & 'hFF == 0;
    f_carry <= tmp_wire & 'h100;
end
endfunction

always @(posedge clk) begin
    compare(op_a, op_b);
end

endmodule // comparator

Answer 1

您不能在 always 块内声明 wire。

wire [7:0] tmp_wire = reg_accumulator - reg_x;

always @(posedge clk) begin
    f_zero <= tmp_wire & 'hFF == 0;
    f_carry <= tmp_wire & 'h100;
end

Answer 2

要么你应该使用 systemverilog 并将其包含在 class 中，要么你可以创建一个参数化模块：

module compare_zero_n_carry
# (
    parameter DATA_WIDTH = 8
  )
(zero, carry, a, b);

  /* ports */
  input [DATA_WIDTH-1:0] a;  //.."reg_accumulator"
  input [DATA_WIDTH-1:0] b;  //.."reg_x"
  output zero;
  output carry;

  wire [DATA_WIDTH-1:0] tmp_wire = a - b;

  assign zero = (tmp_wire & {DATA_WIDTH{1'b1}}) == {DATA_WIDTH{1'b0}};
  //..HERE IM NOT REALLY SURE WHAT IS THE LOGIC FOR THE CARRY,
  //..IT SHOULD BE ONE BIT
  assign carry = (tmp_wire & {1'b1,{(DATA_WIDTH-1){1'b0}}});     
endmodule // compare_zero_n_carry

并在主比较器模块中将其实例化为：

  input                   clk;
  input [DATA_WIDTH-1:0]  op_a;
  input [DATA_WIDTH-1:0]  op_b;

  wire f_zero;
  wire f_carry;
  reg f_zero_reg;
  reg f_carry_reg;

  compare_zero_n_carry
    # (
        .DATA_WIDTH (DATA_WIDTH)
      )
    compare_zero_n_carry_inst (
        .a      (op_a),
        .b      (op_b),
        .zero   (f_zero),
        .carry  (f_carry)
      );

  always @ (posedge clk) begin
    f_zero_reg <= f_zero;
    f_carry_reg <= f_carry;
  end

Verilog 临时变量

Verilog Temporary Variable

verilog

hdl