倒数无符号数每 10 次缺少 9 和 8

Question

我不知道哪里出了问题，也不知道如何解决。我基本上是在构建一个状态计数器，它从 33 开始，在重置之前倒数到 0，但 29、28、19、18、9 和 8 都未命中。我卡在我哪里出错了。

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;


entity sequencer is
 PORT(clk:      IN  std_logic;             
        count   : out unsigned (5 downto 0)); 
End sequencer;

ARCHITECTURE behavior OF sequencer IS
SIGNAL dSig, qSig   : unsigned (5 downto 0);

BEGIN

    PROCESS (clk, dSig)  
    BEGIN 
     
     dSig <= "011011";

    if rising_edge(clk) Then
        qSig <= dSig;
    end if;
     
     if qSig = "000000" then 
       dSig <= "011011"; 
    else
       dSig <= qSig - 1 ; 
    End if;
     
     count <= qSig;
     
    End Process;
END behavior;

Answer 1

我怀疑这是因为您在同一个进程中混合了同步和异步元素，并且小故障导致计数器跳过。我建议让它完全同步。

ARCHITECTURE behavior OF sequencer IS
  SIGNAL count_i   : unsigned (5 downto 0) := (others => '0')

BEGIN

    PROCESS (clk)  
    BEGIN 
        if rising_edge(clk) Then
            count_i <= count_i + 1;
        end if;
    End Process;
 
    count <= count_i;

END behavior;

Answer 2

整个过程可以简化为

process (clk, reset)  
begin 
    if reset then -- use an asynchronous reset for initial value
        dSig <= "011011";

    elsif rising_edge(clk) Then -- keep everything else within the synchronized block
        count <= dSig;
        if dSig = "000000" then
            dSig <= "011011";
        else
            dSig <= dSig - 1 ; 
        end if;
    end if;
end process;

使用一个计数器信号并将所有内容保持在进程的同步块中，或者是否有进行异步输出评估的原因？

倒数无符号数每 10 次缺少 9 和 8

Counting down unsigned numbers is missing the 9 and 8 every 10

vhdl

quartus