ARM64 中堆栈指针的行为
Behaviors of stack pointer in ARM64
由于 ARM64 中缺少 PUSH 和 POP 指令,我无法理解 SP 在 ARM64 中的工作方式。
如果我要 PUSH/POP,SP decrement/increment 是 4、8 还是 16 字节?
我在阅读文档说堆栈帧必须按 16 字节对齐,但是当我调试时,情况似乎并非如此。
堆栈是向上增长还是向下增长完全取决于您正在查看的系统的 ABI。也就是说,我必须处理的所有 arm64 代码都有向下增长的堆栈。
这样,一个普通的推送看起来像这样:
stp x29, x30, [sp, -0x10]!
像这样的普通流行音乐:
ldp x29, x30, [sp], 0x10
这显然 pushes/pops 一次两个寄存器,因此一次修改堆栈指针 16 个字节,这将我们带到下一部分:
堆栈对齐检查。堆栈指针是否必须与 16 字节边界对齐 也 取决于您正在使用的 ABI,但这是一个可以配置的实际硬件功能。
请参阅 the ARMv8 Reference Manual,SCTLR_EL[123]
包括为每个异常级别打开或关闭此功能的位。引自 SCTLR_EL1
,例如:
SA0, bit [4]
SP Alignment check enable for EL0. When set to 1, if a load or store instruction
executed at EL0 uses the SP as the base address and the SP is not aligned to a
16-byte boundary, then a SP alignment fault exception is generated. For more
information, see _SP alignment checking on page D1-2333_.
When ARMv8.1-VHE is implemented, and the value of HCR_EL2.{E2H, TGE} is {1, 1},
this bit has no effect on execution at EL0.
In a system where the PE resets into EL1, this field resets to an architecturally
UNKNOWN value.
SA, bit [3]
SP Alignment check enable. When set to 1, if a load or store instruction executed
at EL1 uses the SP as the base address and the SP is not aligned to a 16-byte
boundary, then a SP alignment fault exception is generated. For more information,
see _SP alignment checking on page D1-2333_.
When ARMv8.1-VHE is implemented, and the value of HCR_EL2.{E2H, TGE} is {1, 1},
this bit has no effect on the PE.
In a system where the PE resets into EL1, this field resets to an architecturally
UNKNOWN value.
由于 ARM64 中缺少 PUSH 和 POP 指令,我无法理解 SP 在 ARM64 中的工作方式。
如果我要 PUSH/POP,SP decrement/increment 是 4、8 还是 16 字节?
我在阅读文档说堆栈帧必须按 16 字节对齐,但是当我调试时,情况似乎并非如此。
堆栈是向上增长还是向下增长完全取决于您正在查看的系统的 ABI。也就是说,我必须处理的所有 arm64 代码都有向下增长的堆栈。
这样,一个普通的推送看起来像这样:
stp x29, x30, [sp, -0x10]!
像这样的普通流行音乐:
ldp x29, x30, [sp], 0x10
这显然 pushes/pops 一次两个寄存器,因此一次修改堆栈指针 16 个字节,这将我们带到下一部分:
堆栈对齐检查。堆栈指针是否必须与 16 字节边界对齐 也 取决于您正在使用的 ABI,但这是一个可以配置的实际硬件功能。
请参阅 the ARMv8 Reference Manual,SCTLR_EL[123]
包括为每个异常级别打开或关闭此功能的位。引自 SCTLR_EL1
,例如:
SA0, bit [4] SP Alignment check enable for EL0. When set to 1, if a load or store instruction executed at EL0 uses the SP as the base address and the SP is not aligned to a 16-byte boundary, then a SP alignment fault exception is generated. For more information, see _SP alignment checking on page D1-2333_. When ARMv8.1-VHE is implemented, and the value of HCR_EL2.{E2H, TGE} is {1, 1}, this bit has no effect on execution at EL0. In a system where the PE resets into EL1, this field resets to an architecturally UNKNOWN value. SA, bit [3] SP Alignment check enable. When set to 1, if a load or store instruction executed at EL1 uses the SP as the base address and the SP is not aligned to a 16-byte boundary, then a SP alignment fault exception is generated. For more information, see _SP alignment checking on page D1-2333_. When ARMv8.1-VHE is implemented, and the value of HCR_EL2.{E2H, TGE} is {1, 1}, this bit has no effect on the PE. In a system where the PE resets into EL1, this field resets to an architecturally UNKNOWN value.