在详细说明时报告抛出类型不匹配错误

Question

我正在尝试调试一些导致可变宽度不匹配问题的错误（下面的添加阶段）。

为此，我想使用report语句输出一些用于计算这些可变宽度的变量。

然而，由于某些原因，即使是最简单的报表语句：

report "this is a message";

正在抛出此错误：

syntax error near report

error type void does not match with a string literal

知道是什么原因造成的吗？

我在 Xilinx Vivado 中使用 VHDL2008。

整个源文件供参考：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.All;
use IEEE.math_real.all;
use work.functions.all;


entity averager is
    generic
    (
        buffer_len: positive := 32; -- MUST BE A POWER OF 2
        input_max: positive := integer'high / buffer_len -- Maximum value of one data input
    );
    port 
    (
        clk : in STD_LOGIC;
        tri : in STD_LOGIC; 
        reset: in std_logic;       
        data_in : in unsigned (get_min_counter_width(input_max) - 1 downto 0);
        avg_out : out unsigned (get_min_counter_width(input_max) - 1 downto 0)
     );
end averager;

architecture behavioral of averager is
    
    -- TODO - Add assert that buffer_len is power of 2


    constant input_width: positive := get_min_counter_width(input_max);
    constant accum_width: positive := get_min_counter_width(input_width * buffer_len); -- Done at synthesis time, perfomance non-critical
    constant avg_bitshift: positive := integer(ceil(log2(real(buffer_len)))); -- How much bitshift is needed for fast divide
    
    signal last_tri: std_logic := '0';
    
    subtype in_val is unsigned(input_width - 1 downto 0);
    type acc_buffer is array(buffer_len - 1 downto 0) of in_val;
    
    constant in_zero: in_val := to_unsigned(0,input_width);
    signal in_buffer: acc_buffer; -- Initialised in reset

    type state is (rst, idle, adding, writing);
    signal current_state: state := rst;
    signal next_state: state := rst;
    
    constant accum_zero: unsigned(accum_width - 1 downto 0) := to_unsigned(0,accum_width);
    signal accumulator: unsigned(accum_width - 1 downto 0) := accum_zero;
    

begin


    sync_proc: process(clk)
    begin
       if (rising_edge(clk)) then
           if (reset = '1') then
               last_tri <= '0';
                current_state <= rst;
            else
                last_tri <= tri;
                current_state <= next_state;
                if (last_tri = '0' and tri = '1') then
                    in_buffer <= in_buffer(in_buffer'high downto in_buffer'low + 1) & in_val(data_in);
                end if;
            end if;
        end if;
    end process;
    
    next_state_decode: process(current_state, tri)
    begin
       next_state <= current_state;
       case(current_state) is
           when rst =>
               next_state <= idle;
           when idle => 
               if (last_tri = '0' and tri = '1') then
                   next_state <= adding;
               end if;
           when adding =>
                   next_state <= writing;
           when writing =>
                   next_state <= idle;     
       end case;
    end process;
    
    output_decode: process(current_state)
    begin
       next_state <= current_state;
       case(current_state) is
           when rst =>
               next_state <= idle;
               for i in in_buffer'high downto 0 loop
                    in_buffer(i) <= in_zero;
               end loop;
           when idle => 

           when adding =>
               for i in in_buffer'high downto 0 loop
                    accumulator <= unsigned(accumulator) + resize(unsigned(in_buffer(i)),accum_width);
               end loop;
           when writing =>
                   avg_out <= accumulator(accumulator'high downto accumulator'low + avg_bitshift);     
       end case;
    end process;
    
    
    report "this is a message";
    


end behavioral;

Answer 1

report 语句是顺序语句，只能在顺序块中使用。

您不能在架构代码中使用 report 语句，它仅适用于并发语句。

report 语句本身就是一个顺序语句。

一个assert语句可以在并发块中使用。如果断言为假，将打印断言 report 子句中的消息。

VHDL 有一个常量，false，布尔类型，值为 False。因此，如果使用 assert false，则将始终打印 report 子句中的消息。

因此，如果您想在并发块中打印消息，也可以使用 assert false report "your message";。

在详细说明时报告抛出类型不匹配错误

Report throwing type mismatch error at elaboration

vhdl