RISC-V 链接描述文件中的访问权限

Question

在编写基于 ARM 的微控制器时，我习惯于在链接描述文件中看到一个 MEMORY{..} 段，如下所示：

MEMORY
{ 
    FLASH (rx): ORIGIN = 0x08000000, LENGTH = 128K
    RAM (xrw): ORIGIN = 0x20000000, LENGTH = 32K
}

访问权限很容易理解：

r: 阅读
w: 写
x: 执行

我正在基于 RISC-V 的微控制器领域迈出第一步。来自 GigaDevice 的 GD32VF103CBT6 微控制器在其链接脚本中具有以下 MEMORY{..} 段：

MEMORY
{ 
    /* Run in FLASH */ 
    flash (rxai!w) : ORIGIN = 0x08000000, LENGTH = 64k
    ram   (wxa!ri) : ORIGIN = 0x20000000, LENGTH = 20k 

    /* Run in RAM */ 
    /* flash (rxai!w) : ORIGIN = 0x20000000, LENGTH = 15k */
    /* ram   (wxa!ri) : ORIGIN = 0x20003C00, LENGTH = 5K  */
}

我应该如何解释这些访问权限？

Answer 1

它们并不是真正的“访问权限”，而是“什么样的部分可以放在这里”。

来自 GNU LD documentation（在 quotint 过程中出现了一些格式错误：

The attr string must consist only of the following characters:

‘R’
Read-only section

‘W’
Read/write section

‘X’
Executable section

‘A’
Allocatable section

‘I’
Initialized section

‘L’
Same as ‘I’

‘!’
Invert the sense of any of the attributes that follow

If an unmapped section matches any of the listed attributes other than ‘!’, it will be placed in the memory region. The ‘!’ attribute reverses the test for the characters that follow, so that an unmapped section will be placed in the memory region only if it does not match any of the attributes listed afterwards. Thus an attribute string of ‘RW!X’ will match any unmapped section that has either or both of the ‘R’ and ‘W’ attributes, but only as long as the section does not also have the ‘X’ attribute.

有了那个背景，我会解释你的配置如下：

flash (rxai!w) : ORIGIN = 0x08000000, LENGTH = 64k

...意味着“flash”区域可以包含除可写部分之外的任何内容，并且

ram   (wxa!ri) : ORIGIN = 0x20000000, LENGTH = 20k

...意味着“ram”区域可以包含除 read-only 和初始化部分之外的任何内容。

RISC-V 链接描述文件中的访问权限

Access rights in RISC-V linkerscripts

embedded

microcontroller

riscv

linker-scripts

riscv32