Error: ordered port connections cannot be mixed with named port connections

Question

我尝试在 Verilog HDL 中实现半加器。我成功地写出了设计源文件，但在测试平台中实例化我的模块时遇到错误。是什么导致了问题？

设计在这里：

module half_adder(a,b,sum,carry);

 input a,b;
 output sum,carry;

 assign sum=a^b;
 assign carry=a&b;

endmodule

测试台是：

实例化语法有什么问题？

Answer 1

去掉最后一个信号后的尾随逗号。变化：

.carry(c),

至：

.carry(c)

Answer 2

你在 .carry(c)

之后多了一个 ","

`include "half_adder.v"

module half_adder_tb;

    reg i0,i1;
    wire s,c;

    half_adder HAI (
        .a(i0),
        .b(i1),
        .sum(s),
        .carry(c)
    )

endmodule;

Error: ordered port connections cannot be mixed with named port connections

Error: ordered port connections cannot be mixed with named port connections

verilog

hdl