VHDL: for...loop 而不是 for...generate

Question

您好，我在使用 for...loop 而不是 for...generate 时遇到问题。我想使用 for...loop 因为我们的教授只教过我们。

library ieee;
use ieee.std_logic_1164.all;

entity supersomm_4bit is
  port (
    c_in: in std_logic;
    a,b: in std_logic_vector(3 downto 0);
    s: out std_logic_vector(3 downto 0);
    sP,sG: out std_logic
  );
end supersomm_4bit;

architecture arch of supersomm_4bit is
  signal p,g,c: std_logic_vector(3 downto 0);

  begin
    g1: for i in 0 to 3 generate
      g(i) <= a(i) and b(i);
      p(i) <= a(i) or b(i);
    end generate;

    c(0) <= c_in;
    c(1) <= g(0) or (p(0) and c(0));
    c(2) <= g(1) or (p(1) and g(0)) or (p(1) and p(0) and c(0));
    c(3) <= g(2) or (p(2) and g(1)) or (p(2) and p(1) and g(0))
            or (p(2) and p(1) and p(0) and c(0));

    g2: for i in 0 to 3 generate
      s(i) <= a(i) xor b(i) xor c(i);
    end generate;

    sP <= p(0) and p(1) and p(2) and p(3);
    sG <= g(3) or (p(3) and g(2)) or (p(3) and p(2) and g(1))
          or (p(3) and p(2) and p(1) and g(0));
end arch;

我试过这样做

architecture for_loop of supersomm_4bit is
  signal p,g,c: std_logic_vector(3 downto 0);
  begin
    process begin
        for i in 0 to 3 loop
        g(i) <= a(i) and b(i);
        p(i) <= a(i) or b(i);
        end loop;
        wait;
    end process;

    c(0) <= c_in;
    c(1) <= g(0) or (p(0) and c(0));
    c(2) <= g(1) or (p(1) and g(0)) or (p(1) and p(0) and c(0));
    c(3) <= g(2) or (p(2) and g(1)) or (p(2) and p(1) and g(0))
            or (p(2) and p(1) and p(0) and c(0));
        
    process begin
        for i in 0 to 3 loop
        s(i) <= a(i) xor b(i) xor c(i);
        end loop;
        wait;
    end process;

    sP <= p(0) and p(1) and p(2) and p(3);
    sG <= g(3) or (p(3) and g(2)) or (p(3) and p(2) and g(1))
            or (p(3) and p(2) and p(1) and g(0));
end architecture for_loop;

但它不起作用（s 和 sP/sG 未初始化）。我也试过将所有代码放在一个进程下，但它仍然不起作用。我是在做错什么，还是应该避免使用 for...loop？谢谢！

编辑（添加整个项目）：

library ieee;
use ieee.std_logic_1164.all;

entity unita_cla is
  port (
    a,b: in std_logic_vector(15 downto 0);
    c_in: in std_logic;
    S: out std_logic_vector(15 downto 0);
    C_OUT: out std_logic
  );
end unita_cla;

architecture arch of unita_cla is
  signal C: std_logic_vector(4 downto 1);
  signal P,G: std_logic_vector(3 downto 0);

  component supersomm_4bit
    port (
      c_in: in std_logic;
      a,b: in std_logic_vector(3 downto 0);
      s: out std_logic_vector(3 downto 0);
      sP,sG: out std_logic
    );
  end component;

  begin
    C(1) <= G(0) or (P(0) and c_in);
    C(2) <= G(1) or (P(1) and G(0)) or (P(1) and P(0) and c_in);
    C(3) <= G(2) or (P(2) and G(1)) or (P(2) and P(1) and G(0))
            or (P(2) and P(1) and P(0) and c_in);
    C(4) <= G(3) or (P(3) and G(2)) or (P(3) and P(2) and G(1))
            or (P(3) and P(2) and P(1) and G(0))
            or (P(3) and P(2) and P(1) and P(0) and c_in);

    bit0_3: supersomm_4bit port map (c_in, a(3 downto 0), b(3 downto 0),
                                     S(3 downto 0), P(0), G(0));
    bit4_7: supersomm_4bit port map (C(1), a(7 downto 4), b(7 downto 4),
                                     S(7 downto 4), P(1), G(1));
    bit8_11: supersomm_4bit port map (C(2), a(11 downto 8), b(11 downto 8),
                                     S(11 downto 8), P(2), G(2));
    bit12_15: supersomm_4bit port map (C(3), a(15 downto 12), b(15 downto 12),
                                     S(15 downto 12), P(3), G(3));

    C_OUT <= C(4);
end arch;

测试台：

library ieee;
use ieee.std_logic_1164.all;

entity unita_cla_tb is
end unita_cla_tb;

architecture testbench of unita_cla_tb is
  signal a,b,S: std_logic_vector(15 downto 0);
  signal c_in,C_OUT: std_logic;

  component unita_cla
    port (
      a,b: in std_logic_vector(15 downto 0);
      c_in: in std_logic;
      S: out std_logic_vector(15 downto 0);
      C_OUT: out std_logic
    );
  end component;

  begin
    u1: unita_cla port map (a,b,c_in,S,C_OUT);
    tb: process
    begin
      a <= "0000000000000000";
      b <= "0000000000000000";
      c_in <= '1';
      wait for 10 ns;
      a <= "1111111111111111";
      b <= "0000000000000000";
      c_in <= '0';
      wait for 10 ns;
      a <= "1010101010101010";
      b <= "0101010101010101";
      c_in <= '1';
      wait for 10 ns;
      a <= "1111111111111111";
      b <= "1111111111111111";
      c_in <= '0';
      wait for 10 ns;
      a <= "1010101010101010";
      b <= "1010101010101010";
      c_in <= '1';
      wait for 10 ns;
      wait;
    end process;
  end testbench;

Answer 1

for supersomm_4bit架构的for循环版本中的两个进程由于无条件等待语句只执行一次。添加敏感度列表并删除等待语句：

architecture for_loop of supersomm_4bit is
    signal p,g,c: std_logic_vector(3 downto 0);
begin
    process (a, b)  -- ADDED sensitiity list
    begin
        for i in 0 to 3 loop
            g(i) <= a(i) and b(i);
            p(i) <= a(i) or b(i);
        end loop;
        -- wait;  -- resumes for every change in a or b
    end process;

    c(0) <= c_in;
    c(1) <= g(0) or (p(0) and c(0));
    c(2) <= g(1) or (p(1) and g(0)) or (p(1) and p(0) and c(0));
    c(3) <= g(2) or (p(2) and g(1)) or (p(2) and p(1) and g(0))
            or (p(2) and p(1) and p(0) and c(0));

    process  (a, b, c)  -- ADDED sensitivity list
    begin
        for i in 0 to 3 loop
        s(i) <= a(i) xor b(i) xor c(i);
        end loop;
        -- wait;   -- resumes for every change in a, b or c
    end process;

    sP <= p(0) and p(1) and p(2) and p(3);
    sG <= g(3) or (p(3) and g(2)) or (p(3) and p(2) and g(1))
            or (p(3) and p(2) and p(1) and g(0));
end architecture for_loop;

允许模拟匹配建筑拱形。每个进程将恢复敏感列表中具有事件（新值）的任何信号。

IEEE 标准 1076-2008
11.3 过程语句

If a process sensitivity list appears following the reserved word process, then the process statement is assumed to contain an implicit wait statement as the last statement of the process statement part; this implicit wait statement is of the form

wait on sensitivity_list ;

构建敏感列表的规则在 10.2 Wait 语句中找到。

14.7.5 模型执行
14.7.5.1 一般

The execution of a model consists of an initialization phase followed by the repetitive execution of process statements in the description of that model. Each such repetition is said to be a simulation cycle. In each cycle, the values of all signals in the description are computed. If as a result of this computation an event occurs on a given signal, process statements that are sensitive to that signal will resume and will be executed as part of the simulation cycle.

At certain stages during the initialization phase and each simulation cycle, the current time, Tc, and the time of the next simulation cycle, Tn, are calculated. Tn is calculated by setting it to the earliest of ...

14.7.5.2 初始化

At the beginning of initialization, the current time, Tc, is assumed to be 0 ns.

The initialization phase consists of the following steps:

.. f) For each nonpostponed process P in the model, the following actions occur in the indicated order:

The process executes until it suspends.
...

进程在等待语句中挂起和恢复。具有敏感列表的进程将隐式等待语句作为最后一个语句。

10.2 等待语句

The timeout clause specifies the maximum amount of time the process will remain suspended at this wait statement. If no timeout clause appears, the timeout clause for (STD.STANDARD.TIME'HIGH – STD.STANDARD.NOW) is assumed. It is an error if the time expression in the timeout clause evaluates to a negative value.

现有的等待语句没有超时子句，会导致进程在初始化后的第一次进程执行后停止执行。用于为信号输出提供更新波形的输入值此时将全部为'U'。

14.7.5.3模拟周期

A simulation cycle consists of the following steps:

...
f) The following actions occur in the indicated order:

...
2) For each process, P, if P is currently sensitive to a signal, S, and if an event has occurred on S in this simulation cycle, then P resumes

在当前模拟时间安排和更新。

VHDL: for...loop 而不是 for...generate

VHDL: for...loop instead of for...generate

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