无法在 Verilog 中创建 'real' 类型数组

Can't create a 'real' type array in Verilog

我尝试在 Icarus Verilog 中按以下方式创建 'real' 类型值数组:

parameter width = 10;
shortreal b [width-1:0] = {0.0181,0.0487,0.1227,0.1967,0.2273,0.1967,0.1227,0.0487,0.0181};

出现以下错误:

error: Cannot assign to array b. Did you forget a word index?

我查看了 icarus verilog src 代码错误消息,对此的解释是“特殊情况:左值是整个内存或数组 slice”。事实上,这是 l 值的错误。检测 通过注意索引计数是否小于 array dimensions (unpacked)”,我认为这意味着数组索引大小与声明的索引大小不同[width-1:0],如果我理解的话这不是真的。

我也试过:

parameter width = 10;
parameter [32:0] b [width-1:0] = {0.0181,0.0487,0.1227,0.1967,0.2273,0.1967,0.1227,0.0487,0.0181};

但没有成功。

使用带有 -g2012 标志的 Icarus Verilog(用于 SV 支持)

只有在填满整个数组的情况下,才可以使用 so-called 数组连接。您的数组有 10 个元素,但右侧只有 9 个:

parameter width = 10;
shortreal b [width-1:0] = {0.0181,0.0487,0.1227,0.1967,0.2273,0.1967,0.1227,0.0487,0.0181,0.0181};