Quartus 网表优化在状态机中丢失寄存器扇出

Question

大家好，我正在尝试实现一个状态机，但我遇到了一个问题，在时序模拟过程中我收到一条错误提示

Info: 1 registers lost all their fanouts during netlist optimizations. The first 1 are displayed below.

Info: Register "state.STATE_I" lost all its fanouts during netlist optimizations.

并且在波形时序模拟中，输出工作正常，但如果我尝试检查实际状态，我只会得到一个初始状态（状态 I）和一个“未定义”在实际状态应该是的其余地方显示，代码为：

library ieee;
use ieee.std_logic_1164.all;
--define entity
entity pregunta1a is
  port(
    resetn  : in  std_logic;
    clock   : in  std_logic;
    w       : in  std_logic;
    z       : out std_logic
  );
end pregunta1a;
--define architecture
architecture behavior of pregunta1a is
  type STATE_TYPE is (STATE_A,STATE_B,STATE_C,STATE_D,STATE_E,STATE_F,STATE_I); -- todos los estados
  signal state, next_state : STATE_TYPE;
begin
  process(clock)
  begin
    if(rising_edge(clock)) then
      if (resetn='0') then
        state <= STATE_I;                
      else
        state <= next_state;
      end if;
    end if;
  end process;
  
  process(state,w) -- complete sensitivity list
  begin
    z<='0';
    case state is
      when  STATE_A =>
        if (w = '1') then
          next_state <= STATE_B;
        else
          next_state <= STATE_C;
        end if;
      when STATE_B =>
        if (w = '1') then
          next_state <= STATE_D;
        else
          next_state <= STATE_A;
        end if;
      when STATE_C =>
        if (w = '1') then
          next_state <= STATE_B;
        else
          next_state <= STATE_E;
        end if;
      when STATE_D =>
        if (w = '1') then
          next_state <= STATE_F;
        else
          next_state <= STATE_A;
        end if;
      when STATE_E =>
        if (w = '1') then
          next_state <= STATE_B;
        else
          next_state <= STATE_E;
          z<='1';  
        end if;
      when STATE_F =>
        if (w = '1') then
          next_state <= STATE_F;
          z<='1';        
        else
          next_state <= STATE_A;
        end if;
      when STATE_I =>
        if (w = '1') then
          next_state <= STATE_B;
        else
          next_state <= STATE_A;
        end if;
    end case;
  end process; 
end behavior;

This is a screenshot of the timing simulation 有人知道如何解决这个问题吗？？

Answer 1

我找到了解决问题的方法，看来我必须强制与丢失的寄存器进行某种类型的交互 (state_I)。我已经更改了代码的某些部分并对其进行了排序以使其更加清晰：

library ieee;
use ieee.std_logic_1164.all;
--define entity
entity pregunta1a is
  port(
    resetn  : in  std_logic;
    clock   : in  std_logic;
    w       : in  std_logic;
    z       : out std_logic
  );
end pregunta1a;
--define architecture
architecture behavior of pregunta1a is
  type STATE_TYPE is (STATE_A,STATE_B,STATE_C,STATE_E,STATE_F,STATE_G,STATE_R); -- todos los estados
  signal state, next_state : STATE_TYPE:=state_R;
begin
  process(clock)
  begin
    if(rising_edge(clock)) then
      if (resetn='0') then
        state <= STATE_R;                
      else
        state <= next_state;
      end if;
    end if;
  end process;
  
  process(state,w,resetn) -- complete sensitivity list
  begin
    z<='0';
    next_state<=state_R;
    case state is
      when  STATE_A =>
        if (w = '0') then
          next_state <= STATE_B;
        else
          next_state <= STATE_E;
        end if;
      when STATE_B =>
        if (w = '0') then
          next_state <= STATE_C;
        else
          next_state <= STATE_E;
        end if;
      when STATE_C =>
        if (w = '0') then
          next_state <= STATE_C;
          z<='1';
        else
          next_state <= STATE_E;
        end if;
      when STATE_E =>
        if (w = '0') then
          next_state <= STATE_A;
        else
          next_state <= STATE_F;
        end if;
      when STATE_F =>
        
        if (w = '0') then
          next_state <= STATE_A;
        else
          next_state <= STATE_G;
        end if;
      when STATE_G =>
        if (w = '0') then
          next_state <= STATE_A;
        else
          next_state <= STATE_G;
          z<='1';        
        end if;
      when STATE_R =>
        if(resetn='1') then
        if (w = '0') then
          next_state <= STATE_A;
        else
          next_state <= STATE_E;
        end if;
        else
          next_state<=state_R;
        end if;
    end case;
    
  end process; 
end behavior;

看来我必须强制建立某种类型的交互 STATE_I，程序按原样运行，但其中一个要求是在模拟中摆脱这个问题

Quartus 网表优化在状态机中丢失寄存器扇出

Quartus netlist optimization lost register fanout in a state machine

state-machine

vhdl

quartus