VHDL 代码中 5 位输入 rom 的数组长度不正确
Improper array length of a 5-bit input rom on VHDL code
我正在尝试创建一个 5 位输入 32 位输出 rom,但在测试台部分我收到一条错误消息,内容如下:
COMP96 ERROR COMP96_0367: "Improper array length (8). Expected length is 5." "testbench.vhd" 18 26
COMP96 ERROR COMP96_0367: "Improper array length (8). Expected length is 5." "testbench.vhd" 17 26
COMP96 ERROR COMP96_0367: "Improper array length (8). Expected length is 5." "testbench.vhd" 16 14
COMP96 ERROR COMP96_0367: "Improper array length (4). Expected length is 5." "testbench.vhd" 15 26
测试台代码如下:
library IEEE;
use IEEE.std_logic_1164.all;
entity rom_test is
end entity rom_test;
architecture dataflow of rom_test is
signal input_address: std_logic_vector (4 downto 0);
signal output_data: std_logic_vector (31 downto 0);
begin
g1: entity work.rom(dataflow)
port map(addr=>input_address, data_out=>output_data);
input_address <= x"0",
x"01" after 20 ns,
x"02" after 40 ns,
x"03" after 60 ns;
end architecture dataflow;
有人可以帮忙吗?
input_address 是长度为 5(4 到 0)的 std_logic_vector。您正在尝试为其分配一个或两位十六进制值,长度为 4 和 8。
解决它的一种方法是将 0 连接到一个十六进制数字,得到一个长度为 5 的向量:
input_address <= '0' & x"0",
'0' & x"1" after 20 ns,
'0' & x"2" after 40 ns,
'0' & x"3" after 60 ns;
另一种方法是只分配input_address的最低4位:
input_address(4) <= '0';
input_address(3 downto 0) <= x"0",
x"1" after 20 ns,
x"2" after 40 ns,
x"3" after 60 ns;
我正在尝试创建一个 5 位输入 32 位输出 rom,但在测试台部分我收到一条错误消息,内容如下:
COMP96 ERROR COMP96_0367: "Improper array length (8). Expected length is 5." "testbench.vhd" 18 26
COMP96 ERROR COMP96_0367: "Improper array length (8). Expected length is 5." "testbench.vhd" 17 26
COMP96 ERROR COMP96_0367: "Improper array length (8). Expected length is 5." "testbench.vhd" 16 14
COMP96 ERROR COMP96_0367: "Improper array length (4). Expected length is 5." "testbench.vhd" 15 26
测试台代码如下:
library IEEE;
use IEEE.std_logic_1164.all;
entity rom_test is
end entity rom_test;
architecture dataflow of rom_test is
signal input_address: std_logic_vector (4 downto 0);
signal output_data: std_logic_vector (31 downto 0);
begin
g1: entity work.rom(dataflow)
port map(addr=>input_address, data_out=>output_data);
input_address <= x"0",
x"01" after 20 ns,
x"02" after 40 ns,
x"03" after 60 ns;
end architecture dataflow;
有人可以帮忙吗?
input_address 是长度为 5(4 到 0)的 std_logic_vector。您正在尝试为其分配一个或两位十六进制值,长度为 4 和 8。
解决它的一种方法是将 0 连接到一个十六进制数字,得到一个长度为 5 的向量:
input_address <= '0' & x"0",
'0' & x"1" after 20 ns,
'0' & x"2" after 40 ns,
'0' & x"3" after 60 ns;
另一种方法是只分配input_address的最低4位:
input_address(4) <= '0';
input_address(3 downto 0) <= x"0",
x"1" after 20 ns,
x"2" after 40 ns,
x"3" after 60 ns;