2位BCD加法器的校验

Question

我用Verilog设计了一个2位BCD加法器。我想自动化验证过程。为此，我在 Verilog 测试台中定义了一组预定义的 input/output 组合。但是，我的测试台运行不正常。

这是我的设计和测试平台：

设计


    `define XLSB X[3:0]
    `define XMSB X[7:4]
    `define YLSB Y[3:0]
    `define YMSB Y[7:4]
    `define Z0 Z[3:0]
    `define Z1 Z[7:4]
    `define Z2 Z[11:8]
    module bcdadder(X,Y,Z);
    input [7:0] X;
    input [7:0] Y;
    output [11:0] Z;
    wire [4:0]S0;
    wire [4:0]S1;
    wire C;
    assign S0=`XLSB+`YLSB;
    assign `Z0=(S0>9) ? S0[3:0]+6 : S0[3:0];
    assign C=(S0>9) ? 1'b1:1'b0;
    assign S1=`XMSB+`YMSB+ C;
    assign `Z1=(S1>9) ? (S1[3:0]+6) : S1[3:0];
    assign `Z2=(S1>9) ? 4'b0001 : 4'b0000 ;
    endmodule

测试平台


    module tb_bcdadder;
    reg [7:0] X_1;
    reg [7:0] Y_1;
    wire [11:0] Z_1;
    reg [7:0] X_1_Array[0:9];
    reg [7:0] Y_1_Array[0:9];
    reg [11:0] result[0:9]; 
    
    initial begin
    
    X_1_Array[0] = 38;
    X_1_Array[1] = 39;
    X_1_Array[2] = 40;
    X_1_Array[3] = 41;
    X_1_Array[4] = 42;
    X_1_Array[5] = 43;
    X_1_Array[6] = 44;
    X_1_Array[7] = 45;
    X_1_Array[8] = 46;
    X_1_Array[9] = 47;
    
    Y_1_Array[0] = 48;
    Y_1_Array[1] = 49;
    Y_1_Array[2] = 50;
    Y_1_Array[3] = 51;
    Y_1_Array[4] = 52;
    Y_1_Array[5] = 53;
    Y_1_Array[6] = 54;
    Y_1_Array[7] = 55;
    Y_1_Array[8] = 56;
    Y_1_Array[9] = 57;
    
     result[0]=86;
     result[1]=88;
     result[2]=90;
     result[3]=92;
     result[4]=94;
     result[5]=96;
     result[6]=98;
     result[7]=100;
     result[8]=102;
     result[9]=104;
     end
    integer i;
    
    bcdadder b1(.X(X_1),.Y(Y_1),.Z(Z_1));
    always begin
            
        for(i = 0; i <= 9; i=i+1)
        begin
            $display(i);
            X_1[7:4] <= X_1_Array[i][7:4];
            X_1[3:0] <= X_1_Array[i][3:0];
            Y_1[7:4] <= Y_1_Array[i][7:4];
            Y_1[3:0] <= Y_1_Array[i][3:0];
            #(40);
            if((result[i][11:8] == Z_1[11:8]) && (result[i][7:4] == Z_1[7:4]) && (result[i][3:0] == Z_1[3:0]))
            begin
                $display("Correct!!!");
            end
            else begin
                $display("Wrong!!!");
            end
        end
        $display("Test Finished");
        $finish();
    end
    initial begin
    $monitor("T=%0t Y=%d X=%d result=%d",$time,Y_1,X_1,Z_1);
    $dumpfile("adder1.vcd");
    $dumpvars(1);
    end
    
    endmodule

日志


    vu2swz@PPLP02:~/Desktop/fpga/top_down$ ./a.out 
              0
    VCD info: dumpfile adder1.vcd opened for output.
    T=0 Y= 48 X= 38 result=  86
    Correct!!!
              1
    T=40 Y= 49 X= 39 result=  88
    Correct!!!
              2
    T=80 Y= 50 X= 40 result=  96
    Wrong!!!
              3
    T=120 Y= 51 X= 41 result=  98
    Wrong!!!
              4
    T=160 Y= 52 X= 42 result= 100
    Wrong!!!
              5
    T=200 Y= 53 X= 43 result= 102
    Wrong!!!
              6
    T=240 Y= 54 X= 44 result= 104
    Wrong!!!
              7
    T=280 Y= 55 X= 45 result= 106
    Wrong!!!
              8
    T=320 Y= 56 X= 46 result= 108
    Wrong!!!
              9
    T=360 Y= 57 X= 47 result= 110
    Wrong!!!
    Test Finished

为什么我的输出是错误的？我觉得我的设计是正确的。

Answer 1

如果您的设计是正确的，那么您的测试平台中的 result 数组是不正确的。

对于验证，最好始终创建设计模型，以便计算预期值。我展示了如何在测试台中使用 function 作为设计行为的参考模型。当我运行模拟时，我总是看到Correct!!!。

module tb_bcdadder;
    reg [7:0] X_1;
    reg [7:0] Y_1;
    wire [11:0] Z_1;
    reg [7:0] X_1_Array[0:9];
    reg [7:0] Y_1_Array[0:9];
    reg [11:0] result;

initial begin
    X_1_Array[0] = 38;
    X_1_Array[1] = 39;
    X_1_Array[2] = 40;
    X_1_Array[3] = 41;
    X_1_Array[4] = 42;
    X_1_Array[5] = 43;
    X_1_Array[6] = 44;
    X_1_Array[7] = 45;
    X_1_Array[8] = 46;
    X_1_Array[9] = 47;

    Y_1_Array[0] = 48;
    Y_1_Array[1] = 49;
    Y_1_Array[2] = 50;
    Y_1_Array[3] = 51;
    Y_1_Array[4] = 52;
    Y_1_Array[5] = 53;
    Y_1_Array[6] = 54;
    Y_1_Array[7] = 55;
    Y_1_Array[8] = 56;
    Y_1_Array[9] = 57;
end

integer i;

bcdadder b1(.X(X_1),.Y(Y_1),.Z(Z_1));

always begin
    for (i = 0; i <= 9; i=i+1) begin
        $display(i);
        X_1 <= X_1_Array[i];
        Y_1 <= Y_1_Array[i];
        #(40);
        result = bcd_add(X_1, Y_1);
        if (Z_1 === result) begin
            $display("Correct!!!");
        end else begin
            $display("Wrong!!! i=%0d result=%0d, Z_1=%0d", i, result, Z_1);
        end
    end
    $display("Test Finished");
    $finish();
end

initial begin
    $monitor("T=%0t Y=%d X=%d result=%d",$time,Y_1,X_1,Z_1);
    $dumpfile("adder1.vcd");
    $dumpvars(1);
end

function [11:0] bcd_add (input [7:0] a, b);
    reg [4:0] S0;
    reg [4:0] S1;
    reg C;
    begin
        S0 = a[3:0] + b[3:0];
        C  = (S0>9);
        S1 = a[7:4] + b[7:4] + C;
        bcd_add[3:0]  = (S0>9) ? (S0[3:0]+6) : S0[3:0];
        bcd_add[7:4]  = (S1>9) ? (S1[3:0]+6) : S1[3:0];
        bcd_add[11:8] = (S1>9) ? 4'b0001 : 4'b0000;
    end
endfunction

endmodule

2位BCD加法器的校验

Verification of 2-digit BCD adder

verilog

fpga