使用加载输入验证 up_down 计数器

Question

我有一个 up_down 带负载计数器的工作设计 input.I 已经验证了功能 manually.I 需要自动化设计验证所以我创建了一个数组，其中包含必要的计数器值。

但是由于某些未知原因，设计验证失败。

这是我的设计


    module up_counter_load(count,load_input,load,enable,clk,reset,up_down,incr_decr );
    output [3:0] count;
    input [3:0] load_input;
    input [3:0]incr_decr;
    input load, enable, clk, reset,up_down;
    reg [3:0] count;
    always @(reset or load_input)
    begin
        if(reset == 0)
            count <= count + 4'b0;
    end
    always @(posedge clk)
        if (reset) begin
            count <= 4'b0 ;
        end else if (load) begin
            count <= load_input;
        end else if (enable) begin
            if (up_down) begin
                count <= count + incr_decr;
            end else begin
                count <= count - incr_decr;
            end
        end
        endmodule

测试台


        module counter_tb;
        reg load,enable,clk,reset,up_down;
        reg [3:0] load_input,incr_decr;
        wire[3:0] count;
        reg[3:0] count_out[1:8];
        reg[3:0] tmp_array[1:8];
        integer i;
        always #5 clk = ~clk;
        initial begin
            count_out[1] = 4'b0000;
            count_out[2] = 4'b0010;
            count_out[3] = 4'b0100;
            count_out[4] = 4'b0110;
            count_out[5] = 4'b1000;
            count_out[6] = 4'b1010;
            count_out[7] = 4'b1100;
            count_out[8] = 4'b1110;
        end
        up_counter_load dut(.count(count),.load_input(load_input),.load(load),.enable(enable),.clk(clk),.reset(reset),.up_down(up_down),.incr_decr(incr_decr));
    
        initial begin
    
            $dumpfile("dump.vcd");
            $dumpvars;
            clk <=1;
            reset <= 1;
            enable <= 0;
            load <= 0;
            up_down <=0;
            #5
    
            up_down <=1;
            reset <= 0;
            enable <= 1;
            load_input <=4'b1111;
            incr_decr <=4'b0010;
            for(i =1; i<=8;i=i+1)
            begin
                #(5);
                tmp_array[i] = count;
                if(tmp_array[i] == count_out[i]) begin
                    $display("Passed!..");
                    $display("count =%b count_out =%b",count,count_out[i]);
                end
                else begin
                    $display("failed!...");
                    $display("count =%b count_out =%b",count,count_out[i]);
                end
            end
            $display("Verification Finished  for up_count");
            #150
        up_down = 0;
        for(i=8;i>=1;i = i-1)
        begin
            tmp_array[i] = count;
            if(tmp_array[i] == count_out[i]) begin
                $display("Passed!..");
                $display("count =%b count_out =%b",count,count_out[i]);
            end
            else begin
                $display("failed!...");
                $display("count =%b count_out =%b",count,count_out[i]);
            end
        end
        $display("Verification Finished for down_count ");
        #300 $finish;
    end
    endmodule

日志


    VCD info: dumpfile dump.vcd opened for output.
    Passed!..
    count =0000 count_out =0000
    Passed!..
    count =0010 count_out =0010
    failed!...
    count =0010 count_out =0100
    failed!...
    count =0100 count_out =0110
    failed!...
    count =0100 count_out =1000
    failed!...
    count =0110 count_out =1010
    failed!...
    count =0110 count_out =1100
    failed!...
    count =1000 count_out =1110
    Verification Finished  for up_count
    failed!...
    count =0110 count_out =1110
    failed!...
    count =0110 count_out =1100
    failed!...
    count =0110 count_out =1010
    failed!...
    count =0110 count_out =1000
    Passed!..
    count =0110 count_out =0110
    failed!...
    count =0110 count_out =0100
    failed!...
    count =0110 count_out =0010
    failed!...
    count =0110 count_out =0000
    Verification Finished for down_count

我不明白自动化验证有什么问题。

Answer 1

注意你的时钟是用

驱动的

always #5 clk = ~clk;

这将每 10 个时间单位产生一个时钟边沿。

在你的检查循环中你有

            for(i =1; i<=8;i=i+1)
            begin
                #(5);
                // runs every 5 units
            end

你应该在那里延迟 #(10)。但最好的做法是有一个 @(posedge clk)，然后如果你改变频率，你就不会破坏测试平台。

使用加载输入验证 up_down 计数器

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