我如何在 vhdl 中使用 "with-select"？
how can i use "with-select" in vhdl?
你好 :) 我仍然对 vhdl 不感兴趣，并尝试使用 with-select 来实现以下内容，但是在对我的 FBGA 实施时我得到了错误的逻辑，我不知道缺少了什么，但不知何故它很棘手，它会如果有人能告诉我我漏掉了重点，那就太好了...
我要实现的是
o0 = ((非i3)和i1和i0)或((非i3)和(非i2)和i1)或(i0和(非i2))或(i3和(非i0))
o1 = ((不是 i0) 和 i3) 或 ((不是 i3) 和 (不是 i2) 和 i1) 或 (i0 和 i2 以及 i3 和 i1)
o2 = (i0 and i2 and i3 and i1) or ((not i3) and (not i1)) or (i3 and (not i1))
o3 = ((i3) and (not i0)) or ((not i3) and (not i2) and i1) or ((not i3) and (not i3) and (not i0 and i1)
我正在尝试重建 PROM ... 我的 vhdl 代码是：
library ieee;
use ieee.std_logic_1164.all;
entity with_select is
port(i3,i2,i1,i0 : in std_logic;
o0,o1,o2,o3:out std_logic
);
end with_select;
architecture behave of with_select is
signal s_out : std_logic_vector(3 downto 0);
begin
with i0 select
o0<=((not i3) and i1 and i0) or ((not i3) and (not i2) and i1) or (i0 and (not i2)) or (i3 and (not i0)) when '1',
'0' when others;
with i1 select
o1<=((not i0) and i3) or ((not i3) and (not i2) and i1) or (i0 and i2 and i3 and i1) when '1',
'0' when others;
with i2 select
o2<=(i0 and i2 and i3 and i1) or ((not i3) and (not i1)) or (i3 and (not i1)) when '1',
'0' when others;
with i3 select
o3<=((i3) and (not i0)) or ((not i3) and (not i2) and i1) or ((not i3) and i0 and i1) when '1',
'0' when others;
end behave;
使用选定的信号赋值语句时，布尔表达式的术语不正确。例如，选择“1”需要在 o0 的赋值中要求 i0 为“1”，这与条款相矛盾：
with i0 select
o0 <= ((not i3) and i1 and i0) or
((not i3) and (not i2) and i1) or
(i0 and (not i2)) or
(i3 and (not i0)) when '1',
'0' when others;
可以通过修改术语在选定的信号分配中更正此要求：
-- selected signal assignment statement with corrected terms
with to_x01(i0) select
o0s <=
-- ((not i3) and i1 and i0) or
(not i3 and i1) or
-- ((not i3) and (not i2) and i1) or -- met in new term above
-- (i0 and (not i2)) or -- as well as new term below
not i2
-- (i3 and (not i0))
when '1',
(not i3 and not i2 and i1) or
i3
when '0',
'X' when others; -- because std_logic;
但翻译起来很费力
还有两种其他类型的赋值也可以：
-- conditional signal assignment statement equivalent
o0c <= '1' when (
(not i3 and i1 and i0) or
(not i3 and not i2 and i1) or
(i0 and not i2) or
(i3 and not i0)
) = '1' else
'0';
-- simple signal assignment statement
o0d <= (not i3 and i1 and i0) or
(not i3 and not i2 and i1) or
(i0 and not i2) or
(i3 and not i0);
您可以证明原始选择的信号赋值语句与布尔表达式不匹配：
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity with_select_tb is
end entity;
architecture foo of with_select_tb is
signal i0, i1, i2, i3: std_logic;
signal o0: std_logic; -- original result
signal o0s: std_logic; -- corrected selected signal assignment
signal o0c: std_logic; -- conditional signal assignment
signal o0d: std_logic; -- dataflow simple waveform assignment
-- for revision less than -2008:
function to_string (inp: std_logic_vector) return string is
variable image_str: string (1 to inp'length);
alias input_str: std_logic_vector (1 to inp'length) is inp;
begin
for i in input_str'range loop
image_str(i) := character'VALUE(std_ulogic'IMAGE(input_str(i)));
end loop;
return image_str;
end function;
begin
-- original selected signal assignment
with i0 select
o0 <= ((not i3) and i1 and i0) or
((not i3) and (not i2) and i1) or
(i0 and (not i2)) or
(i3 and (not i0)) when '1',
'0' when others;
-- selected signal assignment statement with corrected terms
with to_x01(i0) select
o0s <=
-- ((not i3) and i1 and i0) or
(not i3 and i1) or
-- ((not i3) and (not i2) and i1) or -- met in new term above
-- (i0 and (not i2)) or -- as well as new term below
not i2
-- (i3 and (not i0))
when '1',
(not i3 and not i2 and i1) or
i3
when '0',
'X' when others; -- because std_logic;
-- conditional signal assignment statement equivalent
o0c <= '1' when (
(not i3 and i1 and i0) or
(not i3 and not i2 and i1) or
(i0 and not i2) or
(i3 and not i0)
) = '1' else
'0';
-- simple signal assignment statement
o0d <= (not i3 and i1 and i0) or
(not i3 and not i2 and i1) or
(i0 and not i2) or
(i3 and not i0);
STIMULI:
process
begin
report LF & HT & "(i3, i2, i1, i0)" & HT &
"o0 " & "o0s " & "o0c " & "o0d ";
for i in 0 to 15 loop
(i3, i2, i1, i0) <= std_logic_vector(to_unsigned(i,4));
wait for 10 ns;
report LF & HT & to_string(std_logic_vector'(i3, i2, i1, i0)) &
HT & HT & HT &
std_ulogic'image(o0) & " " &
std_ulogic'image(o0s) & " " &
std_ulogic'image(o0c) & " " &
std_ulogic'image(o0d);
end loop;
wait;
end process;
end architecture foo;
产生：
ghdl -r with_select_tb
with_select.vhdl:92:9:@0ms:(report note):
(i3, i2, i1, i0) o0 o0s o0c o0d
with_select.vhdl:97:13:@10ns:(report note):
0000 '0' '0' '0' '0'
with_select.vhdl:97:13:@20ns:(report note):
0001 '1' '1' '1' '1'
with_select.vhdl:97:13:@30ns:(report note):
0010 '0' '1' '1' '1'
with_select.vhdl:97:13:@40ns:(report note):
0011 '1' '1' '1' '1'
with_select.vhdl:97:13:@50ns:(report note):
0100 '0' '0' '0' '0'
with_select.vhdl:97:13:@60ns:(report note):
0101 '0' '0' '0' '0'
with_select.vhdl:97:13:@70ns:(report note):
0110 '0' '0' '0' '0'
with_select.vhdl:97:13:@80ns:(report note):
0111 '1' '1' '1' '1'
with_select.vhdl:97:13:@90ns:(report note):
1000 '0' '1' '1' '1'
with_select.vhdl:97:13:@100ns:(report note):
1001 '1' '1' '1' '1'
with_select.vhdl:97:13:@110ns:(report note):
1010 '0' '1' '1' '1'
with_select.vhdl:97:13:@120ns:(report note):
1011 '1' '1' '1' '1'
with_select.vhdl:97:13:@130ns:(report note):
1100 '0' '1' '1' '1'
with_select.vhdl:97:13:@140ns:(report note):
1101 '0' '0' '0' '0'
with_select.vhdl:97:13:@150ns:(report note):
1110 '0' '1' '1' '1'
with_select.vhdl:97:13:@160ns:(report note):
1111 '0' '0' '0' '0'
简单的信号分配类似于原始布尔表达式。您可以在出现的一元非运算符及其操作数周围提供括号以匹配样式。 VHDL 将 not 优先于其他逻辑运算符，并且不需要括号。
注意报告语句格式依赖于 VHDL 工具实现。
你好 :) 我仍然对 vhdl 不感兴趣，并尝试使用 with-select 来实现以下内容，但是在对我的 FBGA 实施时我得到了错误的逻辑，我不知道缺少了什么，但不知何故它很棘手，它会如果有人能告诉我我漏掉了重点，那就太好了...
我要实现的是
o0 = ((非i3)和i1和i0)或((非i3)和(非i2)和i1)或(i0和(非i2))或(i3和(非i0))
o1 = ((不是 i0) 和 i3) 或 ((不是 i3) 和 (不是 i2) 和 i1) 或 (i0 和 i2 以及 i3 和 i1)
o2 = (i0 and i2 and i3 and i1) or ((not i3) and (not i1)) or (i3 and (not i1))
o3 = ((i3) and (not i0)) or ((not i3) and (not i2) and i1) or ((not i3) and (not i3) and (not i0 and i1)
我正在尝试重建 PROM ... 我的 vhdl 代码是：
library ieee;
use ieee.std_logic_1164.all;
entity with_select is
port(i3,i2,i1,i0 : in std_logic;
o0,o1,o2,o3:out std_logic
);
end with_select;
architecture behave of with_select is
signal s_out : std_logic_vector(3 downto 0);
begin
with i0 select
o0<=((not i3) and i1 and i0) or ((not i3) and (not i2) and i1) or (i0 and (not i2)) or (i3 and (not i0)) when '1',
'0' when others;
with i1 select
o1<=((not i0) and i3) or ((not i3) and (not i2) and i1) or (i0 and i2 and i3 and i1) when '1',
'0' when others;
with i2 select
o2<=(i0 and i2 and i3 and i1) or ((not i3) and (not i1)) or (i3 and (not i1)) when '1',
'0' when others;
with i3 select
o3<=((i3) and (not i0)) or ((not i3) and (not i2) and i1) or ((not i3) and i0 and i1) when '1',
'0' when others;
end behave;
使用选定的信号赋值语句时，布尔表达式的术语不正确。例如，选择“1”需要在 o0 的赋值中要求 i0 为“1”，这与条款相矛盾：
with i0 select
o0 <= ((not i3) and i1 and i0) or
((not i3) and (not i2) and i1) or
(i0 and (not i2)) or
(i3 and (not i0)) when '1',
'0' when others;
可以通过修改术语在选定的信号分配中更正此要求：
-- selected signal assignment statement with corrected terms
with to_x01(i0) select
o0s <=
-- ((not i3) and i1 and i0) or
(not i3 and i1) or
-- ((not i3) and (not i2) and i1) or -- met in new term above
-- (i0 and (not i2)) or -- as well as new term below
not i2
-- (i3 and (not i0))
when '1',
(not i3 and not i2 and i1) or
i3
when '0',
'X' when others; -- because std_logic;
但翻译起来很费力
还有两种其他类型的赋值也可以：
-- conditional signal assignment statement equivalent
o0c <= '1' when (
(not i3 and i1 and i0) or
(not i3 and not i2 and i1) or
(i0 and not i2) or
(i3 and not i0)
) = '1' else
'0';
-- simple signal assignment statement
o0d <= (not i3 and i1 and i0) or
(not i3 and not i2 and i1) or
(i0 and not i2) or
(i3 and not i0);
您可以证明原始选择的信号赋值语句与布尔表达式不匹配：
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity with_select_tb is
end entity;
architecture foo of with_select_tb is
signal i0, i1, i2, i3: std_logic;
signal o0: std_logic; -- original result
signal o0s: std_logic; -- corrected selected signal assignment
signal o0c: std_logic; -- conditional signal assignment
signal o0d: std_logic; -- dataflow simple waveform assignment
-- for revision less than -2008:
function to_string (inp: std_logic_vector) return string is
variable image_str: string (1 to inp'length);
alias input_str: std_logic_vector (1 to inp'length) is inp;
begin
for i in input_str'range loop
image_str(i) := character'VALUE(std_ulogic'IMAGE(input_str(i)));
end loop;
return image_str;
end function;
begin
-- original selected signal assignment
with i0 select
o0 <= ((not i3) and i1 and i0) or
((not i3) and (not i2) and i1) or
(i0 and (not i2)) or
(i3 and (not i0)) when '1',
'0' when others;
-- selected signal assignment statement with corrected terms
with to_x01(i0) select
o0s <=
-- ((not i3) and i1 and i0) or
(not i3 and i1) or
-- ((not i3) and (not i2) and i1) or -- met in new term above
-- (i0 and (not i2)) or -- as well as new term below
not i2
-- (i3 and (not i0))
when '1',
(not i3 and not i2 and i1) or
i3
when '0',
'X' when others; -- because std_logic;
-- conditional signal assignment statement equivalent
o0c <= '1' when (
(not i3 and i1 and i0) or
(not i3 and not i2 and i1) or
(i0 and not i2) or
(i3 and not i0)
) = '1' else
'0';
-- simple signal assignment statement
o0d <= (not i3 and i1 and i0) or
(not i3 and not i2 and i1) or
(i0 and not i2) or
(i3 and not i0);
STIMULI:
process
begin
report LF & HT & "(i3, i2, i1, i0)" & HT &
"o0 " & "o0s " & "o0c " & "o0d ";
for i in 0 to 15 loop
(i3, i2, i1, i0) <= std_logic_vector(to_unsigned(i,4));
wait for 10 ns;
report LF & HT & to_string(std_logic_vector'(i3, i2, i1, i0)) &
HT & HT & HT &
std_ulogic'image(o0) & " " &
std_ulogic'image(o0s) & " " &
std_ulogic'image(o0c) & " " &
std_ulogic'image(o0d);
end loop;
wait;
end process;
end architecture foo;
产生：
ghdl -r with_select_tb
with_select.vhdl:92:9:@0ms:(report note):
(i3, i2, i1, i0) o0 o0s o0c o0d
with_select.vhdl:97:13:@10ns:(report note):
0000 '0' '0' '0' '0'
with_select.vhdl:97:13:@20ns:(report note):
0001 '1' '1' '1' '1'
with_select.vhdl:97:13:@30ns:(report note):
0010 '0' '1' '1' '1'
with_select.vhdl:97:13:@40ns:(report note):
0011 '1' '1' '1' '1'
with_select.vhdl:97:13:@50ns:(report note):
0100 '0' '0' '0' '0'
with_select.vhdl:97:13:@60ns:(report note):
0101 '0' '0' '0' '0'
with_select.vhdl:97:13:@70ns:(report note):
0110 '0' '0' '0' '0'
with_select.vhdl:97:13:@80ns:(report note):
0111 '1' '1' '1' '1'
with_select.vhdl:97:13:@90ns:(report note):
1000 '0' '1' '1' '1'
with_select.vhdl:97:13:@100ns:(report note):
1001 '1' '1' '1' '1'
with_select.vhdl:97:13:@110ns:(report note):
1010 '0' '1' '1' '1'
with_select.vhdl:97:13:@120ns:(report note):
1011 '1' '1' '1' '1'
with_select.vhdl:97:13:@130ns:(report note):
1100 '0' '1' '1' '1'
with_select.vhdl:97:13:@140ns:(report note):
1101 '0' '0' '0' '0'
with_select.vhdl:97:13:@150ns:(report note):
1110 '0' '1' '1' '1'
with_select.vhdl:97:13:@160ns:(report note):
1111 '0' '0' '0' '0'
简单的信号分配类似于原始布尔表达式。您可以在出现的一元非运算符及其操作数周围提供括号以匹配样式。 VHDL 将 not 优先于其他逻辑运算符，并且不需要括号。
注意报告语句格式依赖于 VHDL 工具实现。