alu.v:55: syntax: error: Invalid module instantiation and it say "I give up."
alu.v:55: syntax: error: Invalid module instantiation and it say "I give up."
我的ALU_1bit是对的，我测试过
但是，我的alu有问题。我该如何解决？
alu.v:55: syntax error
alu.v:55: error: Invalid module instantiation
I give up.
ALU_1bit code
timescale 1ns/1ps
module ALU_1bit(
input src1, //1 bit source 1 (input)
input src2, //1 bit source 2 (input)
input Ainvert, //1 bit A_invert (input)
input Binvert, //1 bit B_invert (input)
input Cin, //1 bit carry in (input)
input [2-1:0] operation, //2 bit operation (input)
output reg result, //1 bit result (output)
output reg cout //1 bit carry out (output)
);
reg temp1;
reg temp2;
reg temp3;
reg temp4;
reg temp5;
always@(src1 or src2 or Ainvert or Binvert or Cin or operation)
begin
case (Ainvert)
1'b0: temp1 = src1; // 0
1'b1: temp1 = ~src1; // 1
endcase
//$display("temp1 %d", temp1);
case (Binvert)
1'b0: temp2 = src2; // 0
1'b1: temp2 = ~src2; // 1
endcase
//$display("temp2 %d", temp2);
temp3 = temp1 & temp2;
temp4 = temp1 | temp2;
{cout, temp5} = temp1 + temp2 + Cin;
//$display("temp3 %d", temp3);
//$display("temp4 %d", temp4);
//$display("temp5 %d", temp5);
case (operation)
2'b00: result = temp3; // AND
2'b01: result = temp4; // OR
2'b10: result = temp5; // addition
2'b11: result = temp5; // addition
endcase
end
endmodule
alu code
timescale 1ns/1ps
module alu(
input rst_n, // negative reset (input)
input [32-1:0] src1, // 32 bits source 1 (input)
input [32-1:0] src2, // 32 bits source 2 (input)
input [ 4-1:0] ALU_control, // 4 bits ALU control input (input)
output reg [32-1:0] result, // 32 bits result (output)
output reg zero, // 1 bit when the output is 0, zero must be set (output)
output reg cout, // 1 bit carry out (output)
output reg overflow // 1 bit overflow (output)
);
wire carryout0, carryout1, carryout2, carryout3, carryout4, carryout5, carryout6, carryout7, carryout8, carryout9, carryout10, carryout11, carryout12, carryout13, carryout14, carryout15, carryout16, carryout17, carryout18, carryout19, carryout20, carryout21, carryout22, carryout23, carryout24, carryout25, carryout26, carryout27, carryout28, carryout29, carryout30;
ALU_1bit UUT0(src1[0], src2[0], ALU_control[3], ALU_control[2], ALU_control[2], ALU_control[1:0], result[0], carry0);
ALU_1bit UUT1(src1[1], src2[1], ALU_control[3], ALU_control[2], carry0, ALU_control[1:0], result[1], carry1);
ALU_1bit UUT2(src1[2], src2[2], ALU_control[3], ALU_control[2], carry1, ALU_control[1:0], result[2], carry2);
ALU_1bit UUT3(src1[3], src2[3], ALU_control[3], ALU_control[2], carry2, ALU_control[1:0], result[3], carry3);
ALU_1bit UUT4(src1[4], src2[4], ALU_control[3], ALU_control[2], carry3, ALU_control[1:0], result[4], carry4);
ALU_1bit UUT5(src1[5], src2[5], ALU_control[3], ALU_control[2], carry4, ALU_control[1:0], result[5], carry5);
ALU_1bit UUT6(src1[6], src2[6], ALU_control[3], ALU_control[2], carry5, ALU_control[1:0], result[6], carry6);
ALU_1bit UUT7(src1[7], src2[7], ALU_control[3], ALU_control[2], carry6, ALU_control[1:0], result[7], carry7);
ALU_1bit UUT8(src1[8], src2[8], ALU_control[3], ALU_control[2], carry7, ALU_control[1:0], result[8], carry8);
ALU_1bit UUT9(src1[9], src2[9], ALU_control[3], ALU_control[2], carry8, ALU_control[1:0], result[9], carry9);
ALU_1bit UUT10(src1[10], src2[10], ALU_control[3], ALU_control[2], carry9, ALU_control[1:0], result[10], carry10);
ALU_1bit UUT11(src1[11], src2[11], ALU_control[3], ALU_control[2], carry10, ALU_control[1:0], result[11], carry11);
ALU_1bit UUT12(src1[12], src2[12], ALU_control[3], ALU_control[2], carry11, ALU_control[1:0], result[12], carry12);
ALU_1bit UUT13(src1[13], src2[13], ALU_control[3], ALU_control[2], carry12, ALU_control[1:0], result[13], carry13);
ALU_1bit UUT14(src1[14], src2[14], ALU_control[3], ALU_control[2], carry13, ALU_control[1:0], result[14], carry14);
ALU_1bit UUT15(src1[15], src2[15], ALU_control[3], ALU_control[2], carry14, ALU_control[1:0], result[15], carry15);
ALU_1bit UUT16(src1[16], src2[16], ALU_control[3], ALU_control[2], carry15, ALU_control[1:0], result[16], carry16);
ALU_1bit UUT17(src1[17], src2[17], ALU_control[3], ALU_control[2], carry16, ALU_control[1:0], result[17], carry17);
ALU_1bit UUT18(src1[18], src2[18], ALU_control[3], ALU_control[2], carry17, ALU_control[1:0], result[18], carry18);
ALU_1bit UUT19(src1[19], src2[19], ALU_control[3], ALU_control[2], carry18, ALU_control[1:0], result[19], carry19);
ALU_1bit UUT20(src1[20], src2[20], ALU_control[3], ALU_control[2], carry19, ALU_control[1:0], result[20], carry20);
ALU_1bit UUT21(src1[21], src2[21], ALU_control[3], ALU_control[2], carry20, ALU_control[1:0], result[21], carry21);
ALU_1bit UUT22(src1[22], src2[22], ALU_control[3], ALU_control[2], carry21, ALU_control[1:0], result[22], carry22);
ALU_1bit UUT23(src1[23], src2[23], ALU_control[3], ALU_control[2], carry22, ALU_control[1:0], result[23], carry23);
ALU_1bit UUT24(src1[24], src2[24], ALU_control[3], ALU_control[2], carry23, ALU_control[1:0], result[24], carry24);
ALU_1bit UUT25(src1[25], src2[25], ALU_control[3], ALU_control[2], carry24, ALU_control[1:0], result[25], carry25);
ALU_1bit UUT26(src1[26], src2[26], ALU_control[3], ALU_control[2], carry25, ALU_control[1:0], result[26], carry26);
ALU_1bit UUT27(src1[27], src2[27], ALU_control[3], ALU_control[2], carry26, ALU_control[1:0], result[27], carry27);
ALU_1bit UUT28(src1[28], src2[28], ALU_control[3], ALU_control[2], carry27, ALU_control[1:0], result[28], carry28);
ALU_1bit UUT29(src1[29], src2[29], ALU_control[3], ALU_control[2], carry28, ALU_control[1:0], result[29], carry29);
ALU_1bit UUT30(src1[30], src2[30], ALU_control[3], ALU_control[2], carry29, ALU_control[1:0], result[30], carry30);
ALU_1bit UUT31(src1[31], src2[31], ALU_control[3], ALU_control[2], carry30, ALU_control[1:0], result[31], cout);
always@(rst_n)
zero = ~(result[0]|result[1]|result[2]|result[3]|result[4]|result[5]|result[6]|result[7]|result[8]|result[9]|result[10]|result[11]|result[12]|result[13]|result[14]|result[15]|result[16]|result[17]|result[18]|result[19]|result[20]|result[21]|result[22]|result[23]|result[24]|result[25]|result[26]|result[27]|result[28]|result[29]|result[30]|result[31]);
overflow = result[31] ^ cout;
end
endmodule
我得到 3 个编译错误。
您不得在 alu 模块中将 result 和 cout 声明为 reg，因为您从模块实例输出中驱动它们。只需使用这个：
output [32-1:0] result, // 32 bits result (output)
output cout, // 1 bit carry out (output)
此外，您需要将 begin 添加到您的 always 块
always@(rst_n) begin
zero = ~(result[0]|result[1]|result[2]|result[3]|result[4]|result[5]|result[6]|result[7]|result[8]|result[9]|result[10]|result[11]|result[12]|result[13]|result[14]|result[15]|result[16]|result[17]|result[18]|result[19]|result[20]|result[21]|result[22]|result[23]|result[24]|result[25]|result[26]|result[27]|result[28]|result[29]|result[30]|result[31]);
overflow = result[31] ^ cout;
end
在这种情况下，分配给 zero 的更简单方法是使用归约或运算符：
zero = ~(|result);
我的ALU_1bit是对的，我测试过
但是，我的alu有问题。我该如何解决？
alu.v:55: syntax error
alu.v:55: error: Invalid module instantiation
I give up.
ALU_1bit code
timescale 1ns/1ps
module ALU_1bit(
input src1, //1 bit source 1 (input)
input src2, //1 bit source 2 (input)
input Ainvert, //1 bit A_invert (input)
input Binvert, //1 bit B_invert (input)
input Cin, //1 bit carry in (input)
input [2-1:0] operation, //2 bit operation (input)
output reg result, //1 bit result (output)
output reg cout //1 bit carry out (output)
);
reg temp1;
reg temp2;
reg temp3;
reg temp4;
reg temp5;
always@(src1 or src2 or Ainvert or Binvert or Cin or operation)
begin
case (Ainvert)
1'b0: temp1 = src1; // 0
1'b1: temp1 = ~src1; // 1
endcase
//$display("temp1 %d", temp1);
case (Binvert)
1'b0: temp2 = src2; // 0
1'b1: temp2 = ~src2; // 1
endcase
//$display("temp2 %d", temp2);
temp3 = temp1 & temp2;
temp4 = temp1 | temp2;
{cout, temp5} = temp1 + temp2 + Cin;
//$display("temp3 %d", temp3);
//$display("temp4 %d", temp4);
//$display("temp5 %d", temp5);
case (operation)
2'b00: result = temp3; // AND
2'b01: result = temp4; // OR
2'b10: result = temp5; // addition
2'b11: result = temp5; // addition
endcase
end
endmodule
alu code
timescale 1ns/1ps
module alu(
input rst_n, // negative reset (input)
input [32-1:0] src1, // 32 bits source 1 (input)
input [32-1:0] src2, // 32 bits source 2 (input)
input [ 4-1:0] ALU_control, // 4 bits ALU control input (input)
output reg [32-1:0] result, // 32 bits result (output)
output reg zero, // 1 bit when the output is 0, zero must be set (output)
output reg cout, // 1 bit carry out (output)
output reg overflow // 1 bit overflow (output)
);
wire carryout0, carryout1, carryout2, carryout3, carryout4, carryout5, carryout6, carryout7, carryout8, carryout9, carryout10, carryout11, carryout12, carryout13, carryout14, carryout15, carryout16, carryout17, carryout18, carryout19, carryout20, carryout21, carryout22, carryout23, carryout24, carryout25, carryout26, carryout27, carryout28, carryout29, carryout30;
ALU_1bit UUT0(src1[0], src2[0], ALU_control[3], ALU_control[2], ALU_control[2], ALU_control[1:0], result[0], carry0);
ALU_1bit UUT1(src1[1], src2[1], ALU_control[3], ALU_control[2], carry0, ALU_control[1:0], result[1], carry1);
ALU_1bit UUT2(src1[2], src2[2], ALU_control[3], ALU_control[2], carry1, ALU_control[1:0], result[2], carry2);
ALU_1bit UUT3(src1[3], src2[3], ALU_control[3], ALU_control[2], carry2, ALU_control[1:0], result[3], carry3);
ALU_1bit UUT4(src1[4], src2[4], ALU_control[3], ALU_control[2], carry3, ALU_control[1:0], result[4], carry4);
ALU_1bit UUT5(src1[5], src2[5], ALU_control[3], ALU_control[2], carry4, ALU_control[1:0], result[5], carry5);
ALU_1bit UUT6(src1[6], src2[6], ALU_control[3], ALU_control[2], carry5, ALU_control[1:0], result[6], carry6);
ALU_1bit UUT7(src1[7], src2[7], ALU_control[3], ALU_control[2], carry6, ALU_control[1:0], result[7], carry7);
ALU_1bit UUT8(src1[8], src2[8], ALU_control[3], ALU_control[2], carry7, ALU_control[1:0], result[8], carry8);
ALU_1bit UUT9(src1[9], src2[9], ALU_control[3], ALU_control[2], carry8, ALU_control[1:0], result[9], carry9);
ALU_1bit UUT10(src1[10], src2[10], ALU_control[3], ALU_control[2], carry9, ALU_control[1:0], result[10], carry10);
ALU_1bit UUT11(src1[11], src2[11], ALU_control[3], ALU_control[2], carry10, ALU_control[1:0], result[11], carry11);
ALU_1bit UUT12(src1[12], src2[12], ALU_control[3], ALU_control[2], carry11, ALU_control[1:0], result[12], carry12);
ALU_1bit UUT13(src1[13], src2[13], ALU_control[3], ALU_control[2], carry12, ALU_control[1:0], result[13], carry13);
ALU_1bit UUT14(src1[14], src2[14], ALU_control[3], ALU_control[2], carry13, ALU_control[1:0], result[14], carry14);
ALU_1bit UUT15(src1[15], src2[15], ALU_control[3], ALU_control[2], carry14, ALU_control[1:0], result[15], carry15);
ALU_1bit UUT16(src1[16], src2[16], ALU_control[3], ALU_control[2], carry15, ALU_control[1:0], result[16], carry16);
ALU_1bit UUT17(src1[17], src2[17], ALU_control[3], ALU_control[2], carry16, ALU_control[1:0], result[17], carry17);
ALU_1bit UUT18(src1[18], src2[18], ALU_control[3], ALU_control[2], carry17, ALU_control[1:0], result[18], carry18);
ALU_1bit UUT19(src1[19], src2[19], ALU_control[3], ALU_control[2], carry18, ALU_control[1:0], result[19], carry19);
ALU_1bit UUT20(src1[20], src2[20], ALU_control[3], ALU_control[2], carry19, ALU_control[1:0], result[20], carry20);
ALU_1bit UUT21(src1[21], src2[21], ALU_control[3], ALU_control[2], carry20, ALU_control[1:0], result[21], carry21);
ALU_1bit UUT22(src1[22], src2[22], ALU_control[3], ALU_control[2], carry21, ALU_control[1:0], result[22], carry22);
ALU_1bit UUT23(src1[23], src2[23], ALU_control[3], ALU_control[2], carry22, ALU_control[1:0], result[23], carry23);
ALU_1bit UUT24(src1[24], src2[24], ALU_control[3], ALU_control[2], carry23, ALU_control[1:0], result[24], carry24);
ALU_1bit UUT25(src1[25], src2[25], ALU_control[3], ALU_control[2], carry24, ALU_control[1:0], result[25], carry25);
ALU_1bit UUT26(src1[26], src2[26], ALU_control[3], ALU_control[2], carry25, ALU_control[1:0], result[26], carry26);
ALU_1bit UUT27(src1[27], src2[27], ALU_control[3], ALU_control[2], carry26, ALU_control[1:0], result[27], carry27);
ALU_1bit UUT28(src1[28], src2[28], ALU_control[3], ALU_control[2], carry27, ALU_control[1:0], result[28], carry28);
ALU_1bit UUT29(src1[29], src2[29], ALU_control[3], ALU_control[2], carry28, ALU_control[1:0], result[29], carry29);
ALU_1bit UUT30(src1[30], src2[30], ALU_control[3], ALU_control[2], carry29, ALU_control[1:0], result[30], carry30);
ALU_1bit UUT31(src1[31], src2[31], ALU_control[3], ALU_control[2], carry30, ALU_control[1:0], result[31], cout);
always@(rst_n)
zero = ~(result[0]|result[1]|result[2]|result[3]|result[4]|result[5]|result[6]|result[7]|result[8]|result[9]|result[10]|result[11]|result[12]|result[13]|result[14]|result[15]|result[16]|result[17]|result[18]|result[19]|result[20]|result[21]|result[22]|result[23]|result[24]|result[25]|result[26]|result[27]|result[28]|result[29]|result[30]|result[31]);
overflow = result[31] ^ cout;
end
endmodule
我得到 3 个编译错误。
您不得在 alu 模块中将 result 和 cout 声明为 reg，因为您从模块实例输出中驱动它们。只需使用这个：
output [32-1:0] result, // 32 bits result (output)
output cout, // 1 bit carry out (output)
此外，您需要将 begin 添加到您的 always 块
always@(rst_n) begin
zero = ~(result[0]|result[1]|result[2]|result[3]|result[4]|result[5]|result[6]|result[7]|result[8]|result[9]|result[10]|result[11]|result[12]|result[13]|result[14]|result[15]|result[16]|result[17]|result[18]|result[19]|result[20]|result[21]|result[22]|result[23]|result[24]|result[25]|result[26]|result[27]|result[28]|result[29]|result[30]|result[31]);
overflow = result[31] ^ cout;
end
在这种情况下，分配给 zero 的更简单方法是使用归约或运算符：
zero = ~(|result);