Verilog: ERROR:HDLCompiler:806

Question

任务是创建一个 7 位二进制到 bcd 计数器。但是，对于我的模块之一，我收到类似

的错误

ERROR:HDLCompiler:806 - "D:/Xilinx Stuff/Binary_BCD/prog_counter.v" Line 23: Syntax error near "input".

我刚刚开始学习这门语言，希望尽我所能获得语法方面的所有帮助。我四处寻找简单的错误，例如缺少分号，但找不到任何错误。也许第二组眼睛会有所帮助：

module prog_count_7(max_count, reset, clk, count_out)

input [6:0] max_count;
input reset, clk;
output [6:0] count_out;

// Wires/Registers required go here.
reg reset;
reg [6:0] max_count;


// 7-bit counter instance
count_7 counter_1(.enable(1'b1),
          .reset(reset),
          .clk(clk),
          .count_out(count_out));


// logic for Counter control
always @(enable or reset or posedge clk or count_out) begin
    if(reset == 1) begin // Reset Condition
        if(max_count >= 99) begin
            count_out = 99;
        end else if(max_count<99 & count_out <99 & max_count > count_out) begin
            count_out = count_out + 1;
            end
    end else if(reset == 0) begin
        count_out = 0;
        end
end

Answer 1

您在第一行缺少一个分栏。

module prog_count_7(max_count, reset, clk, count_out) <b>; //<-- here</b>

此外，您 "Counter control" 的敏感度列表没有意义。 enable 和 count_out 不应该存在。 reset should benegedge reset`。通常是这样的：

always @(posedge clk or negedge reset)

建议在分配触发器时使用非阻塞（<=）。

"Counter control"

的建议编码

always @(posedge clk or negedge reset) begin
    if (reset == 0) begin // Reset Condition
        count_out <= 0;
    end
    else if (enable == 1) begin
        if (max_count >= 99) begin
            count_out <= 99;
        end
        else if (count_out < 99 && max_count > count_out) begin
            count_out <= count_out + 1;
        end
    end
end

Verilog: ERROR:HDLCompiler:806

Verilog: ERROR:HDLCompiler:806

verilog