尝试用门级代码模拟 JK-FF

Question

我一直在尝试用门级代码模拟 JK-FF，但它不起作用。感谢任何帮助。

线路代码：

module circuit1_3_c(j,k,r,cp,q,q1);
input j,k,r,cp;
output q,q1;
wire t1,t2,t3,t4;

nand(t1,t2,q);
nand(t2,t1,j,cp,t3);
nand(t3,cp,k,t4);
nand(t4,t3,t1);
nand(q,q1,t2);
nand(q1,q,t3,r);

endmodule

测试台代码：

module circuit1_3_ctest;
parameter STEP=10;
parameter HALF_STEP=5;

reg j,k,r,cp;
wire q,q1;
circuit1_3_c circ(j,k,r,cp,q,q1);
initial begin
$dumpfile("circuit1_3_c.vcd");
$dumpvars(0,circuit1_3_ctest);
$monitor("\%t: J=%b, K=%b, R=%b, Cp=%b, Q=%b, Qbar=%b", $time, j,k,r,cp,q,q1);
r<=1'b1;
cp<=1'b0;
j<=1'b0; k<=1'b0; r<=1'b1;
#STEP; 
j<=1'b0; k<=1'b1; r<=1'b1;
#STEP;
j<=1'b1; k<=1'b0; r<=1'b1;
#STEP;
j<=1'b1; k<=1'b1; r<=1'b1;
#STEP;
j<=1'b0; k<=1'b0; r<=1'b1;
#STEP; 
j<=1'b0; k<=1'b1; r<=1'b1;
#STEP;
j<=1'b1; k<=1'b0; r<=1'b1;
#STEP;
j<=1'b1; k<=1'b1; r<=1'b1;
#HALF_STEP
$finish;
end
always #HALF_STEP cp=~cp;     
endmodule

输出。如您所见，q 和 q1 始终未知 (x):

[1

Answer 1

您需要正确重置您的逻辑。一种方法是在时间 0 将 r 驱动为 0。变化：

r<=1'b1;
cp<=1'b0;
j<=1'b0; k<=1'b0; r<=1'b1;

至：

cp<=1'b0;
j<=1'b0; k<=1'b0; r<=1'b0;

输出：

               0: J=0, K=0, R=0, Cp=0, Q=0, Qbar=1
               5: J=0, K=0, R=0, Cp=1, Q=0, Qbar=1
              10: J=0, K=1, R=1, Cp=0, Q=0, Qbar=1
              15: J=0, K=1, R=1, Cp=1, Q=0, Qbar=1
              20: J=1, K=0, R=1, Cp=0, Q=0, Qbar=1
              25: J=1, K=0, R=1, Cp=1, Q=1, Qbar=0
              30: J=1, K=1, R=1, Cp=0, Q=1, Qbar=0
              35: J=1, K=1, R=1, Cp=1, Q=0, Qbar=1
              40: J=0, K=0, R=1, Cp=0, Q=0, Qbar=1
              45: J=0, K=0, R=1, Cp=1, Q=0, Qbar=1
              50: J=0, K=1, R=1, Cp=0, Q=0, Qbar=1
              55: J=0, K=1, R=1, Cp=1, Q=0, Qbar=1
              60: J=1, K=0, R=1, Cp=0, Q=0, Qbar=1
              65: J=1, K=0, R=1, Cp=1, Q=1, Qbar=0
              70: J=1, K=1, R=1, Cp=0, Q=1, Qbar=0

尝试用门级代码模拟 JK-FF

Trying to simulate JK-FF with gate level code

verilog

iverilog