为什么你在我的 VHDL 代码中的“=”中出错
Why are you giving an error in "=" in my VHDL code
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY f_4fir_cont IS
PORT (
rst, clk : IN std_logic;
ctrl : OUT std_logic
);
END f_4fir_cont;
ARCHITECTURE bhvrl OF f_4fir_cont IS TYPE state_enum IS (s0, s1);
SIGNAL state : state_enum := s0;
SIGNAL nexts : state_enum := s1;
BEGIN
clkp : PROCESS (clk, rst)
BEGIN
IF (rst = "0") THEN
state <= s0;
ELSIF (clk'EVENT AND clk = "1" AND
clk'LAST_VALUE = "0") THEN
state <= nexts;
END IF;
END PROCESS clkp;
transp : PROCESS (state)
BEGIN
CASE state IS
WHEN s0 => nexts <= s1;
ctrl <= "0";
WHEN s1 => nexts <= s0;
ctrl <= "1";
END CASE;
END PROCESS transp;
END bhvrl;
我在一本书中找到了这段代码,如果 (rst = "0") THEN 出现此错误:
错误 (10327):f_4fir_cont.vhd(17) 处的 VHDL 错误:无法确定运算符“”=”的定义 -- 找到 0
我已经研究过,但没有发现任何可以解决的问题,我是从 VHDL 开始的,我需要帮助。
rst
和clk
都是std_logic
,是枚举类型。您正在将它们与数组进行比较。将所有比较更改为单个字符:
if rst = '0' then
等等
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY f_4fir_cont IS
PORT (
rst, clk : IN std_logic;
ctrl : OUT std_logic
);
END f_4fir_cont;
ARCHITECTURE bhvrl OF f_4fir_cont IS TYPE state_enum IS (s0, s1);
SIGNAL state : state_enum := s0;
SIGNAL nexts : state_enum := s1;
BEGIN
clkp : PROCESS (clk, rst)
BEGIN
IF (rst = "0") THEN
state <= s0;
ELSIF (clk'EVENT AND clk = "1" AND
clk'LAST_VALUE = "0") THEN
state <= nexts;
END IF;
END PROCESS clkp;
transp : PROCESS (state)
BEGIN
CASE state IS
WHEN s0 => nexts <= s1;
ctrl <= "0";
WHEN s1 => nexts <= s0;
ctrl <= "1";
END CASE;
END PROCESS transp;
END bhvrl;
我在一本书中找到了这段代码,如果 (rst = "0") THEN 出现此错误: 错误 (10327):f_4fir_cont.vhd(17) 处的 VHDL 错误:无法确定运算符“”=”的定义 -- 找到 0 我已经研究过,但没有发现任何可以解决的问题,我是从 VHDL 开始的,我需要帮助。
rst
和clk
都是std_logic
,是枚举类型。您正在将它们与数组进行比较。将所有比较更改为单个字符:
if rst = '0' then
等等