如何重写此 VHDL 代码以防止闩锁？

Question

architecture Behavioral of REGISTERS is

type REG_FILE_TYPE is array(0 to 15) of STD_LOGIC_VECTOR(15 downto 0);


signal REG_ARRAY : REG_FILE_TYPE:= (others => X"0000");
begin
process(WRITE_ENABLE,REG_CLOCK) is
 begin  
 
    case (WRITE_ENABLE) is
        when '1' => REG_ARRAY(to_integer(unsigned(WRITE_ADDRESS))) <= REG_INPUT;
        when '0' => NULL;
        when others => NULL;
    end case;
    
end process;

Answer 1

您忘记将时钟添加到进程中。如果没有时钟，并且合成器推断您需要一些内存来实现，那么除了添加锁存器之外别无选择。这几乎总是一个错误。

除此之外，我不喜欢这里的案例结构，简单的 if-then 就可以了。这就是我实现它的方式：

process(REG_CLOCK) is
  begin  
    if rising_edge(REG_CLOCK) then
      if WRITE_ENABLE = '0' then
        REG_ARRAY(to_integer(unsigned(WRITE_ADDRESS))) <= REG_INPUT;
      end if;
    end if:
end process;

如何重写此 VHDL 代码以防止闩锁？

How do I rewrite this VHDL code to prevent latches?

case

fpga

vhdl

xilinx