由于方向声明导致编译代码出错

Question

我是运行来自互联网的代码使用iverilog如下：

example.v

 module example
      (A,B,C,D,E,F,Y);
wire t1, t2, t3, Y;

nand #1 G1 (t1,A,B);
and  #2 G2 (t2,C,~B,D);
nor  #1 G3 (t3,E,F);
nand #1 G4 (Y,t1,t2,t3);
endmodule

和示例-test.v

 module testbench;
 reg A,B,C,D,E,F; wire Y;
 example DUT(A,B,C,D,E,F,Y);

 initial
 begin
  $monitor ($time," A=%b, B=%b, C=%b, D=%b, E=%b, F=%b, Y=%b", A,B,C,D,E,F,Y);
  #5 A=1; B=0; C=0; D=1; E=0; F=0;
  #5 A=0; B=0; C=1; D=1; E=0; F=0;
  #5 A=1; C=0; D=1; 
  #5 F=1;
  #5 $finish;
  end
 endmodule

我用下面的命令编译它

 iverilog -o mysim example.v example-test.v

并得到以下错误：

 example.v:1: error: Port A (1) of module example has no direction declaration.
 example.v:1: error: Port B (2) of module example has no direction declaration.
 example.v:1: error: Port C (3) of module example has no direction declaration.
 example.v:1: error: Port D (4) of module example has no direction declaration.
 example.v:1: error: Port E (5) of module example has no direction declaration.
 example.v:1: error: Port F (6) of module example has no direction declaration.
 example.v:1: error: Port Y (7) of module example has no direction declaration.
 example.v:2: error: signal A in module testbench.DUT is not a port.
 example.v:2:      : Are you missing an input/output/inout declaration?
 example.v:2: error: signal B in module testbench.DUT is not a port.
 example.v:2:      : Are you missing an input/output/inout declaration?

example.v 代码 incorrect/obsolete 中是否包含完整的 Verilog 语法？为什么我会收到编译错误？

例子取自youtube nptel verilog tutorial

Answer 1

消息告诉您需要在模块 example 中使用方向关键字声明所有模块端口，例如 input 和 output。这修复了错误：

module example
      (A,B,C,D,E,F,Y);
      input A,B,C,D,E,F;
      output Y;
wire t1, t2, t3;

nand #1 G1 (t1,A,B);
and  #2 G2 (t2,C,~B,D);
nor  #1 G3 (t3,E,F);
nand #1 G4 (Y,t1,t2,t3);
endmodule

视频播放大约 28 分钟后，example 代码是正确的，因为它使用了 input 和 output。您复制的代码稍后会出现在视频中，但它是不正确的。

请注意，无需将 Y 声明为 wire。

更简洁的避免端口名称重复的方法如下：

module example (
    input A,B,C,D,E,F,
    output Y
);
wire t1, t2, t3;

nand #1 G1 (t1,A,B);
and  #2 G2 (t2,C,~B,D);
nor  #1 G3 (t3,E,F);
nand #1 G4 (Y,t1,t2,t3);
endmodule

由于方向声明导致编译代码出错

Error compiling code due to direction declaration

verilog

iverilog