VHDL Modelsim：数组长度不匹配（空数组与长度为 8 的数组）

Question

我想知道为什么我的一些 std_logic_vectors 显示为空向量，尤其是当我已经指定长度时。如果有任何帮助，我将不胜感激

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
entity counter8bits is
port(counter_enable, rst, clk : IN std_logic; counter_out : OUT std_logic_vector(7 to 0));
end entity counter8bits;

architecture counting_arc of counter8bits is
signal current_count : std_logic_vector(7 to 0);
type jstate is (nullState, start0, start1, change01, change10);
signal present_state : jstate;
signal next_state: jstate := nullState;



signal int_count: integer := 0;
begin

present_state <= next_state when clk'event and clk = '1';

current_count <= std_logic_vector(to_unsigned(int_count, 8)) when rising_edge(clk);
counter_out <= current_count;
stacking: process(present_state)
begin

next_state <= present_state;
int_count <= 0 when int_count = 255;    
                    case present_state is
                    
                        when nullState =>
                            if counter_enable = '0' then
                                next_state <= start0;
                            else
                                next_state <= start1;
                            end if;
                        
                        when start0 =>
                            if counter_enable = '1' then
                                next_state <= change01;
                                int_count <= int_count + 1;
                            else
                                next_state <= start0;
                            end if;
                        
                        when start1 =>
                            if counter_enable = '0' then
                                next_state <= change10;
                                int_count <= int_count + 1;
                            else
                                next_state <= start1;
                            end if;
                        
                        when change01 =>
                            if counter_enable = '0' then
                                next_state <= change10;
                                int_count <= int_count + 1;
                            else
                                next_state <= start1;
                            end if;
                        
                        when change10 =>
                            if counter_enable = '1' then
                                next_state <= change01;
                                int_count <= int_count + 1;
                            else
                                next_state <= start0;
                            end if;
                        when others =>
                            next_state <= nullState;                    

end case;

end process stacking;
end architecture counting_arc;

这是错误：致命错误：(vsim-3420) 数组长度不匹配。左边是 0（7 到 0（空数组））。右边是 8（7 到 0）。

左指current_count和counter_out

Answer 1

当您以错误的方向指定值时，会出现空范围。此处您已将 current_count 和 counter_out 都指定为 7 to 0。使用 to 是一个升序范围，因此第一个数字应该是较小的。同样，downto 是一个递减范围，左边应该有较高的值。

在这里，我建议您将 to 替换为 downto，因为这是通常的惯例。

VHDL Modelsim：数组长度不匹配（空数组与长度为 8 的数组）

VHDL Modelsim: Array lengths do not match (null array vs array of length 8)

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