初学者在Quartus中编译Verilog的问题

Question

我正在学习 Verilog。我正在尝试创建一个代码，让 LED 以特定频率闪烁。我知道我使用的时钟是 100Mhz，所以我希望它以 1Hz 的周期运行。我为 27 位设置了一个注册表，这应该让我进入 1*10^8.

module main(
        input wire clk,         //100MHz//
        input wire reset_,
        output reg[1:0] LED1        //LED On/Off Two-States//
        );
        reg ON = 1'b1;      //INIT//
        reg[27:0] LEDStateCount;    //LED Counter - 27 Bit Stored//
        reg OFF;            //State of LED//
    
        assign LED1[0] = OFF;       
        assign LED1[1] = ON;
    
        always @(posedge clk or negedge reset_)begin
            if (!reset_)begin
                LEDStateCount <= 27'd0;    //On startup, clear value//
            end
            else if (LEDStateCount<LEDStateCount[27'd50000000])begin
                LEDStateCount <= LEDStateCount + 1;             //Accumulate to ~50,000,000//
                OFF <= LEDStateCount[27'd50000000];             //LED Off Until Value Reached//
            end
        end
    endmodule

我在 Quartus 中编译时遇到错误-

Error (10219): Verilog HDL Continuous Assignment error at Frequencytest.v(10): object "LED1" on left-hand side of assignment must have a net type

Error (10219): Verilog HDL Continuous Assignment error at Frequencytest.v(11): object "LED1" on left-hand side of assignment must have a net type

我认为这与我在注册时声明的内容有关。这是我做这个的时候参考的两页，

Badprog.com - LED Blinking In Verilog

Similar Thread with Blinking LED's

我确定除了那几个语法错误之外，此代码还有其他问题。

Answer 1

错误告诉您不应将 assign 用于 reg 类型。要解决此问题，请更改：

    output reg[1:0] LED1        //LED On/Off Two-States//

至：

    output [1:0] LED1        //LED On/Off Two-States//

我还收到关于 LEDStateCount[27'd50000000].

两种用法的警告

Warning-[SIOB] Select index out of bounds
"LEDStateCount[27'd50000000]"
  The select index is out of declared bounds : [27:0].
  In module : main.

括号中的数字必须在 0 到 27 之间，不能是 50,000,000。

        else if (LEDStateCount<LEDStateCount[27'd50000000])begin

大概应该是这样的：

        else if (LEDStateCount<27'd50000000)begin

初学者在Quartus中编译Verilog的问题

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