注册文件不读取任何数据

Question

我正在尝试设计一个状态机来计算并替换 47 到 58 之间的值。但是在我的波形中，我一直在寄存器文件中为我的 R_data 获取 XXX，因此其余的我的顶层设计被抛弃了。我似乎无法找到 R_data 为 R_en = 1 的任何地址输出 XXX 的原因。我使用的是 Vivado 2020.2；感谢您的帮助，如果我需要澄清任何问题，请告诉我。

注册：

`timescale 1ns / 1ps
module RegFile16x8(R_Addr, W_Addr, R_en, W_en, R_Data, W_Data, Clk, Rst);   
input [3:0] R_Addr, W_Addr;
input Clk, Rst, R_en, W_en;
output reg [7:0] R_Data;
input [7:0] W_Data;
reg [7:0] RegFile [0:15];

always @(posedge Clk) begin
  if (Rst == 1) begin
      RegFile[0] <= 8'd48;
      RegFile[1] <= 8'd53;
      RegFile[2] <= 8'd68;
      RegFile[3] <= 8'd57;
      RegFile[4] <= 8'd55;
      RegFile[5] <= 8'd59;
      RegFile[6] <= 8'd40;
      RegFile[7] <= 8'd49;
      RegFile[8] <= 8'd31;
      RegFile[9] <= 8'd38;
      RegFile[10] <= 8'd54;
      RegFile[11] <= 8'd50;
      RegFile[12] <= 8'd63;
      RegFile[13] <= 8'd58;
      RegFile[14] <= 8'd70;
      RegFile[15] <= 8'd51;
   end
   else if (W_en==1) begin
        RegFile[W_Addr] <= W_Data;
   end
 end

 always @(*) begin
  if (R_en==1)
     R_Data <= RegFile[R_Addr];
  else
     R_Data <= 8'bZZZZZZZZ;
end
endmodule

顶级：

`timescale 1ns / 1ps


module PartA(Clk, Rst, go, done, count);
input Clk, Rst, go;
output reg [6:0] count;
output reg done;
reg [2:0] State, StateNext;
parameter s1 = 0, s2 = 1, s3 = 2, s4 = 3, s5 = 4, s6 = 5, s7 = 6, s8 = 7;

reg [4:0] i; 
reg [7:0] temp;
reg R_en, W_en;
reg [7 :0] a_i;
wire [7:0] a_o;
//RegFile16x8(R_Addr, W_Addr, R_en, W_en, R_Data, W_Data, Clk, Rst);   
RegFile16x8 r1(i[3:0], i[3:0], R_en, W_en, a_o, a_i, Clk, Rst);

always @(State, Rst, count) begin
    R_en = 0;
    W_en = 0;
    case(State)
        s1: begin
            if(go == 1)
                StateNext = s2;
            else
                StateNext = s1;
        end
        s2: begin
            done = 0;
            count = 0;
            i = 0; 
            StateNext = s3;
        end
        s3: begin
            if(i < 16)
                StateNext = s4;
            else    
                StateNext = s5;
        end
        s4: begin
            R_en = 1;
            temp = a_o;
            if ((temp > 47) && (temp < 58))
                StateNext = s7;
            else
                StateNext = s6;
        end
        s5: begin
            done = 1;
            StateNext = s1;
        end
        s6: begin
            StateNext = s8;
        end
        s7: begin
            W_en = 1;
            count = count + 1;
            a_i = temp - 48;
            StateNext = s8;
        end
        s8: begin
            i = i + 1;
            StateNext = s3;
        end
        default: begin
            StateNext = s1;
        end
    endcase
end
always @(posedge Clk) begin
    if (Rst == 1) 
        State = s1;
    else
        State = StateNext;
 end
endmodule

测试台：

`timescale 1ns / 1ps

module partA_tb();

reg Clk, Rst, go;
wire [6:0] count;
wire done;

PartA a1(Clk, Rst, go, done, count);

 always begin 
    Clk = 0;
    #200
    Clk = 1;
    #200;
 end
 initial begin
    Rst = 1;
    #200
    Rst = 0;
    go = 1;
 end

endmodule

Answer 1

您需要在测试台中保持 Rst 更长的时间。 Clk 的第一个姿势发生在时间 200ns，也就是您释放复位的时候。您需要保持复位断言直到时钟的第一个姿势之后才能正确复位您的 RegFile，因为它是同步复位。

此测试平台更改允许 RegFile 重置为已知值：

 initial begin
    Rst = 1;
    #400
    Rst = 0;
    go = 1;
 end

上面的更改从 R_data 中删除了 XXX。

我选择了400的任意延迟，但它可以是任何大于200的东西。关键是你至少需要一个Clk的姿势来采样Rst的时候。

注册文件不读取任何数据

Register file not reading any data

verilog

vivado