未调用 Verilog 模块

Question

我正在开发一个程序，它将采用 BCD 格式的值，将其转换为二进制，并将给定值递减计数为 0。BCD 转换模块工作完美，但似乎我的 'microwave' 模块未被调用。

我这个程序的输出是：

time = xxxxxxxx bcdtime = 0001 0010

time = 00001100 bcdtime = 0001 0010

我可以看到转换，但没有发生倒计时。任何人都可以解释我可能出错的地方或指出可以帮助我回答这个问题的资源方向吗？我的代码如下：

module bcd_to_bin(bintime,bcdtime1,bcdtime0);
  input [3:0] bcdtime1,bcdtime0;
  output [7:0] bintime;

  assign bintime = (bcdtime1 * 4'b1010) + {3'b0, bcdtime0};
endmodule

module microwave(bintimeout, Clk, Start, Stop, bintime, status);
    input [7:0] bintime;
    input Clk, Start, Stop;
    output reg [7:0] bintimeout;
    output reg status;
    
    
 always @ (posedge Start)
    begin
        assign bintimeout = bintime;
    end 
    
 always @ (posedge Clk)

  begin 
    bintimeout = bintimeout - 1;
  end
endmodule


module t_microwave;

    wire status;
    wire [7:0] bintimeout;
    reg Clk=1; reg Start, Stop;
    reg [3:0] bcdtime1, bcdtime0;
    wire [7:0] bintime;
    
    microwave M2 (bintimeout, Clk, Start, Stop, bintime, status);
    bcd_to_bin M3 (bintime,bcdtime1,bcdtime0);
    
    
    
     always #10 Clk = ~Clk;
    initial
      begin
        
        Start = 0; Stop = 0; bcdtime1 = 4'b0001; bcdtime0 = 4'b0010;
        #10 Start = 1; #10 Start = 0;

        
      end       

    initial #10000 $finish;

    initial
      begin
        $monitor ("time = %b, bcdtime = %b %b ", bintimeout, bcdtime1, bcdtime0);
      end
endmodule

Answer 1

您的代码存在一些问题。

如果您想保证您的设计捕获 Start 脉冲，您应该确保它在一个时钟周期 (20) 内处于高电平。变化：

    #10 Start = 1; #10 Start = 0;

至：

    #10 Start = 1; #20 Start = 0;

在microwave模块中，你应该在一个always块中分配给bintimeout，而不是两个，并且不需要在里面使用assign关键字一个 always 块。此外，良好的编码实践建议对顺序逻辑使用非阻塞分配 (<=)。这是编写模块代码的更好方法：

module microwave(bintimeout, Clk, Start, Stop, bintime, status);
    input [7:0] bintime;
    input Clk, Start, Stop;
    output reg [7:0] bintimeout;
    output reg status;
    
    always @ (posedge Clk) begin
        if (Start) begin
            bintimeout <= bintime;
        end else begin
            bintimeout <= bintimeout - 1;
        end
    end
endmodule

这是现在的输出，显示倒计时：

time = xxxxxxxx, bcdtime = 0001 0010 
time = 00001100, bcdtime = 0001 0010 
time = 00001011, bcdtime = 0001 0010 
time = 00001010, bcdtime = 0001 0010 
time = 00001001, bcdtime = 0001 0010 
time = 00001000, bcdtime = 0001 0010 
time = 00000111, bcdtime = 0001 0010 
time = 00000110, bcdtime = 0001 0010 
time = 00000101, bcdtime = 0001 0010 
time = 00000100, bcdtime = 0001 0010 
time = 00000011, bcdtime = 0001 0010 
time = 00000010, bcdtime = 0001 0010 
time = 00000001, bcdtime = 0001 0010 
time = 00000000, bcdtime = 0001 0010 
time = 11111111, bcdtime = 0001 0010 
time = 11111110, bcdtime = 0001 0010

未调用 Verilog 模块

Verilog module not being called

verilog

icarus