为什么 if else 语句不起作用？无论输入X1和X0如何，测试台中Y的输出为0

Question

我正在为下面的状态图编写代码，但不确定为什么我按照正确的顺序得到的输出 Y 为 0？为了测试目的，我测试并将第一次转换 S0 到 S1 的输出 Y 的值更改为 1，第一次转换没有工作，我考虑错了什么？ VHDL

library ieee;
use IEEE.STD_LOGIC_1164.all;

entity seqdet is
 port(
 
 RST,CLK : in STD_LOGIC;  
 X1,X0: in STD_LOGIC;
 Y: out STD_LOGIC
  );

end seqdet;

architecture BHV of seqdet is   
type state is (S0,S1,S2,S3,S4,S5);
signal presentstate, nextstate:state;
begin
CLK_PULSE:process(CLK,RST)
begin 

if rising_edge(CLK) then
if(RST='1') then
presentstate<=S0;
elsif(RST='0') then
presentstate<=nextstate;
end if;
end if;
end process;

state_process:process(presentstate,X1,X0)
begin
if(presentstate<=S0) then
Y<='0';
if(X1='0' and X0='0') then
nextstate<=S1;
else
nextstate<=S0;
end if;

elsif(nextstate<=S1 ) then
Y<='0';
if(X1='0' and X0='0') then
nextstate<=S2;
else
nextstate<=S0;
end if;

elsif(presentstate<=S2 ) then
Y<='0';
if(X1='0' and X0='0') then
nextstate<=S2;
elsif(X1='0' and X0='1') then
nextstate<=S3;
else
nextstate<=S0;
end if;

 elsif(presentstate<=S3 ) then
 Y<='0';
 if(X1='1' and X0='1') then
 nextstate<=S4;
 else
 nextstate<=S0;
 end if;

 elsif(presentstate<=S4 ) then
 Y<='0';
 if(X1='0' and X0='0') then
 nextstate<=S5;
 else
 nextstate<=S0;
 end if;

 elsif(presentstate<=S5 ) then
 if(X1='0' and X0='0') then
 Y<='0';
 nextstate<=S2;
 elsif(X1='1' and X0='0' ) then
 Y<='1';

 nextstate<=S0;
 else
 Y<='0';
 nextstate<=S0;
 end if;

 end if;
 end process;
 end BHV;

测试平台

library ieee;
use IEEE.STD_LOGIC_1164.all;

entity seqdetest is
end seqdetest;

architecture seqdetest_arch of seqdetest is





signal CLK: std_logic:='0';
signal RST: std_logic;
signal X1,X0: std_logic;
signal Y: std_logic;

BEGIN


 uut: entity work.seqdet   
 port map (
      CLK=>CLK,
      RST => RST,
      X1 => X1,
      X0 => X0,
      Y => Y
     
      
     );


 CLK_proc: process
 begin  
  CLK<= '1';
  wait for 50 ns;
 CLK <= '0';
 wait for 50 ns;

end process CLK_proc;      

sim_proc:process
begin
RST<='1';
wait for  100 ns;
RST<='0';
X1<='0';X0<='0';
wait for 100 ns;
X1<='0';X0<='0';
wait for 100 ns;
X1<='0';X0<='1';
wait for 100 ns;
X1<='1';X0<='1';
wait for 100 ns;
X1<='0';X0<='0';
wait for 100 ns;
 X1<='1';X0<='0';
wait for 100 ns;
end process sim_proc;

END seqdetest_arch ;

Answer 1

为了提高可读性，添加了白色 space 并删除了多余的括号。显示为获得 Y = '1' 所做的所有更改：

state_process: 
    process (presentstate, X1, X0)
    begin
        if presentstate = S0 then  -- CHANGED = WAS <=
            Y <= '0';
            if X1 = '0' and X0 = '0' then
                nextstate <= S1;
            else
                nextstate <= S0;
            end if;
        elsif presentstate = S1 then  -- CHANGED presentstate WAS nextstate
                                      -- CHANGED = WAS <=
            Y <= '0';
            if X1 = '0' and X0 = '0' then
                nextstate <= S2;
            else
                nextstate <= S0;
            end if;

        elsif presentstate = S2 then  -- CHANGED = WAS <=
            Y <= '0';
            if X1 = '0' and X0 = '0' then
                nextstate <= S2;
            elsif X1 = '0' and X0 = '1'  then
                nextstate <= S3;
            else
                nextstate <= S0;
            end if;

        elsif presentstate = S3 then  -- CHANGED = WAS <=
            Y <= '0';
            if X1 = '1' and X0 = '1' then
                nextstate <= S4;
            else
                nextstate <= S0;
            end if;

        elsif presentstate = S4 then  -- CHANGED = WAS <=
            Y <= '0';
            if X1 = '0' and X0 = '0' then
                nextstate <= S5;
            else
                nextstate <= S0;
            end if;

        elsif presentstate = S5 then  -- CHANGED = WAS <=
            if X1 = '0' and X0 = '0' then
                Y <= '0';
                nextstate <= S2;
            elsif X1 = '1' and X0 = '0' then
                Y <= '1';
                nextstate <= S0;
            else
                Y <= '0';
                nextstate <= S0;
            end if;
        end if;
     end process;

有一个地方 elsif nextstate = S1 then 应该评估 presentstate，但没有计划更新到 S1。没有干预等待语句。执行任何流程语句时不会发生信号更新。这可能会导致您的分支错误。

所有六个状态评估都使用小于或等于 (<=)，这是不正确的。枚举类型是标量类型并且是有序的。使用小于或等于取决于外部 if 语句（可以用 case 语句替换）中的条件评估顺序。

通过这 7 个更改，您得到 Y = '1':

第一个提到的更改反映了印刷错误。以下六种通常被描述为thinkos。

我发现你的状态图中的分支符号几乎无法理解，并把 VHDL 作为状态图的概念文档，并假设存在错误。 VHDL 旨在记录设计说明。

测试平台不测试 S5 到 S2 分支，也不测试所有到 S0 的分支。

为什么 if else 语句不起作用？无论输入X1和X0如何，测试台中Y的输出为0

Why the if else statement not working? Output of Y in test bench is 0 regardless of input X1 and X0

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