使用 VHDL 实现 DEMUX 的最佳方法是什么？

Question

嗯，我正在学习一些关于数字电路的基础知识，可以说我只是一个初学者。对于我的最终项目，我必须实现一些组件，其中之一是 多路分解器 。实际上，我认为必须有更好的方法来实现它并且我认为我的代码不干净。有没有办法使用 for 循环或 while 来实现它？这是我的代码：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;



entity Demux17 is
    Port ( I : in  STD_LOGIC;
           SEL : in  STD_LOGIC_VECTOR (4 downto 0);
           O : out  STD_LOGIC_VECTOR (16 downto 0));
end Demux17;

architecture Behavioral of Demux17 is

begin
    O(0) <= (I AND NOT SEL(0) AND NOT SEL(1) AND NOT SEL(2) AND NOT SEL(3) AND NOT SEL(4));
    O(1) <= (I AND SEL(0) AND NOT SEL(1) AND NOT SEL(2) AND NOT SEL(3) AND NOT SEL(4));
    O(2) <= (I AND NOT SEL(0) AND SEL(1) AND NOT SEL(2) AND NOT SEL(3) AND NOT SEL(4));
    O(3) <= (I AND SEL(0) AND SEL(1) AND NOT SEL(2) AND NOT SEL(3) AND NOT SEL(4));
    O(4) <= (I AND NOT SEL(0) AND NOT SEL(1) AND SEL(2) AND NOT SEL(3) AND NOT SEL(4));
    O(5) <= (I AND SEL(0) AND NOT SEL(1) AND SEL(2) AND NOT SEL(3) AND NOT SEL(4));
    O(6) <= (I AND NOT SEL(0) AND SEL(1) AND SEL(2) AND NOT SEL(3) AND NOT SEL(4));
    O(7) <= (I AND SEL(0) AND SEL(1) AND SEL(2) AND NOT SEL(3) AND NOT SEL(4));
    O(8) <= (I AND NOT SEL(0) AND NOT SEL(1) AND NOT SEL(2) AND SEL(3) AND NOT SEL(4));
    O(9) <= (I AND SEL(0) AND NOT SEL(1) AND NOT SEL(2) AND SEL(3) AND NOT SEL(4));
    O(10) <= (I AND NOT SEL(0) AND SEL(1) AND NOT SEL(2) AND SEL(3) AND NOT SEL(4));
    O(11) <= (I AND SEL(0) AND SEL(1) AND NOT SEL(2) AND SEL(3) AND NOT SEL(4));
    O(12) <= (I AND NOT SEL(0) AND NOT SEL(1) AND SEL(2) AND SEL(3) AND NOT SEL(4));
    O(13) <= (I AND SEL(0) AND NOT SEL(1) AND SEL(2) AND SEL(3) AND NOT SEL(4));
    O(14) <= (I AND NOT SEL(0) AND SEL(1) AND SEL(2) AND SEL(3) AND NOT SEL(4));
    O(15) <= (I AND SEL(0) AND SEL(1) AND SEL(2) AND SEL(3) AND SEL(4));
    O(16) <= (I AND NOT SEL(0) AND NOT SEL(1) AND NOT SEL(2) AND NOT SEL(3) AND SEL(4));
end Behavioral;

如有任何帮助或建议，我将不胜感激。谢谢

Answer 1

尝试使用您的 SEL 输入作为 O 输出地址的生成语句

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;

entity Demux17 is
    Port ( I : in  STD_LOGIC;
           SEL : in  STD_LOGIC_VECTOR (4 downto 0);
           O : out  STD_LOGIC_VECTOR (16 downto 0));
end Demux17;

architecture Behavioral of Demux17 is

begin
   gen_label: for J in 0 to 16 generate
      O(J) <= I when to_integer(unsigned(SEL)) = J else '0';
   end generate gen_label;
end Behavioral;

使用 VHDL 实现 DEMUX 的最佳方法是什么？

What is the best way to implement a DEMUX using VHDL?

vhdl